DE69423874D1 - Verbessertes Schema zur geordneten Cachespeicherkohärenz - Google Patents

Verbessertes Schema zur geordneten Cachespeicherkohärenz

Info

Publication number
DE69423874D1
DE69423874D1 DE69423874T DE69423874T DE69423874D1 DE 69423874 D1 DE69423874 D1 DE 69423874D1 DE 69423874 T DE69423874 T DE 69423874T DE 69423874 T DE69423874 T DE 69423874T DE 69423874 D1 DE69423874 D1 DE 69423874D1
Authority
DE
Germany
Prior art keywords
cache coherence
improved scheme
ordered cache
ordered
scheme
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69423874T
Other languages
English (en)
Other versions
DE69423874T2 (de
Inventor
Craig R Frink
William R Bryg
Kenneth K Chan
Thomas R Hotchkiss
Robert D Odineal
James B Lowell Williams
Michael L Ziegler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69423874D1 publication Critical patent/DE69423874D1/de
Application granted granted Critical
Publication of DE69423874T2 publication Critical patent/DE69423874T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
DE69423874T 1994-02-24 1994-08-12 Verbessertes Schema zur geordneten Cachespeicherkohärenz Expired - Lifetime DE69423874T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/201,463 US5530933A (en) 1994-02-24 1994-02-24 Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus

Publications (2)

Publication Number Publication Date
DE69423874D1 true DE69423874D1 (de) 2000-05-11
DE69423874T2 DE69423874T2 (de) 2000-11-16

Family

ID=22745920

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69423874T Expired - Lifetime DE69423874T2 (de) 1994-02-24 1994-08-12 Verbessertes Schema zur geordneten Cachespeicherkohärenz

Country Status (6)

Country Link
US (1) US5530933A (de)
EP (1) EP0669578B1 (de)
JP (1) JP3640997B2 (de)
KR (1) KR100371845B1 (de)
DE (1) DE69423874T2 (de)
TW (1) TW260770B (de)

Families Citing this family (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504874A (en) * 1993-09-29 1996-04-02 Silicon Graphics, Inc. System and method of implementing read resources to maintain cache coherency in a multiprocessor environment permitting split transactions
US5813028A (en) * 1993-10-12 1998-09-22 Texas Instruments Incorporated Cache read miss request invalidation prevention method
JP3872118B2 (ja) * 1995-03-20 2007-01-24 富士通株式会社 キャッシュコヒーレンス装置
US5657472A (en) * 1995-03-31 1997-08-12 Sun Microsystems, Inc. Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor
US5787476A (en) * 1995-05-05 1998-07-28 Silicon Graphics, Inc. System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer
US5925099A (en) * 1995-06-15 1999-07-20 Intel Corporation Method and apparatus for transporting messages between processors in a multiple processor system
US6108735A (en) * 1995-09-29 2000-08-22 Intel Corporation Method and apparatus for responding to unclaimed bus transactions
US5659710A (en) * 1995-11-29 1997-08-19 International Business Machines Corporation Cache coherency method and system employing serially encoded snoop responses
US5701422A (en) * 1995-12-13 1997-12-23 Ncr Corporation Method for ensuring cycle ordering requirements within a hierarchical bus system including split-transaction buses
US5673413A (en) * 1995-12-15 1997-09-30 International Business Machines Corporation Method and apparatus for coherency reporting in a multiprocessing system
US5829035A (en) * 1995-12-22 1998-10-27 Apple Computer, Inc. System and method for preventing stale data in multiple processor computer systems
US5717900A (en) * 1996-01-26 1998-02-10 Unisys Corporation Adjusting priority cache access operations with multiple level priority states between a central processor and an invalidation queue
US5765196A (en) * 1996-02-27 1998-06-09 Sun Microsystems, Inc. System and method for servicing copyback requests in a multiprocessor system with a shared memory
JPH11501141A (ja) * 1996-03-15 1999-01-26 サン・マイクロシステムズ・インコーポレーテッド 分割トランザクション・スヌーピング・バスおよび調停方法
US5960179A (en) * 1996-07-01 1999-09-28 Sun Microsystems, Inc. Method and apparatus extending coherence domain beyond a computer system bus
US5790822A (en) * 1996-03-21 1998-08-04 Intel Corporation Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor
US5872941A (en) * 1996-06-05 1999-02-16 Compaq Computer Corp. Providing data from a bridge to a requesting device while the bridge is receiving the data
US6108741A (en) * 1996-06-05 2000-08-22 Maclaren; John M. Ordering transactions
US6035362A (en) * 1996-06-05 2000-03-07 Goodrum; Alan L. Storing data associated with one request while continuing to store data associated with a previous request from the same device
US5987539A (en) * 1996-06-05 1999-11-16 Compaq Computer Corporation Method and apparatus for flushing a bridge device read buffer
US5872939A (en) * 1996-06-05 1999-02-16 Compaq Computer Corporation Bus arbitration
US6055590A (en) * 1996-06-05 2000-04-25 Compaq Computer Corporation Bridge circuit comprising independent transaction buffers with control logic adapted to store overflow data in second buffer when transaction size exceeds the first buffer size
US6075929A (en) * 1996-06-05 2000-06-13 Compaq Computer Corporation Prefetching data in response to a read transaction for which the requesting device relinquishes control of the data bus while awaiting data requested in the transaction
US6052513A (en) * 1996-06-05 2000-04-18 Compaq Computer Corporation Multi-threaded bus master
US6021480A (en) * 1996-06-05 2000-02-01 Compaq Computer Corporation Aligning a memory read request with a cache line boundary when the request is for data beginning at a location in the middle of the cache line
US5903906A (en) * 1996-06-05 1999-05-11 Compaq Computer Corporation Receiving a write request that allows less than one cache line of data to be written and issuing a subsequent write request that requires at least one cache line of data to be written
US5805839A (en) * 1996-07-02 1998-09-08 Advanced Micro Devices, Inc. Efficient technique for implementing broadcasts on a system of hierarchical buses
US5796605A (en) * 1996-07-02 1998-08-18 Sun Microsystems, Inc. Extended symmetrical multiprocessor address mapping
US5963978A (en) * 1996-10-07 1999-10-05 International Business Machines Corporation High level (L2) cache and method for efficiently updating directory entries utilizing an n-position priority queue and priority indicators
JP3210590B2 (ja) 1996-11-29 2001-09-17 株式会社日立製作所 マルチプロセッサシステムおよびキャッシュコヒーレンシ制御方法
US5802355A (en) * 1996-12-10 1998-09-01 International Business Machines Corporation Multi-processor system using processors of different speeds
US5926840A (en) * 1996-12-18 1999-07-20 Unisys Corporation Out-of-order fetching
US5764932A (en) * 1996-12-23 1998-06-09 Intel Corporation Method and apparatus for implementing a dual processing protocol between processors
US6138192A (en) * 1996-12-31 2000-10-24 Compaq Computer Corporation Delivering a request to write or read data before delivering an earlier write request
FR2759178B1 (fr) * 1997-02-05 1999-04-09 Sgs Thomson Microelectronics Circuit de gestion de memoire dans un environnement multi-utilisateurs avec requete et priorite d'acces
US6055608A (en) * 1997-04-14 2000-04-25 International Business Machines Corporation Method and system for speculatively sourcing cache memory data within a multiprocessor data-processing system
US5944805A (en) * 1997-08-21 1999-08-31 Advanced Micro Devices, Inc. System and method for transmitting data upon an address portion of a computer system bus during periods of maximum utilization of a data portion of the bus
US6108752A (en) * 1997-10-24 2000-08-22 Compaq Computer Corporation Method and apparatus for delaying victim writes in a switch-based multi-processor system to maintain data coherency
US6122714A (en) * 1997-10-24 2000-09-19 Compaq Computer Corp. Order supporting mechanisms for use in a switch-based multi-processor system
US6085294A (en) * 1997-10-24 2000-07-04 Compaq Computer Corporation Distributed data dependency stall mechanism
US6154816A (en) * 1997-10-24 2000-11-28 Compaq Computer Corp. Low occupancy protocol for managing concurrent transactions with dependencies
US6070231A (en) * 1997-12-02 2000-05-30 Intel Corporation Method and apparatus for processing memory requests that require coherency transactions
US6003106A (en) * 1998-05-27 1999-12-14 International Business Machines Corporation DMA cache control logic
US6085293A (en) * 1998-08-17 2000-07-04 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that decreases latency by expediting rerun requests
KR100582782B1 (ko) * 1998-08-28 2006-08-23 엘지엔시스(주) 캐쉬 일관성 유지 방법
US6546429B1 (en) * 1998-09-21 2003-04-08 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that holds and reissues requests at a target processing node in response to a retry
US6067603A (en) * 1998-10-01 2000-05-23 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that speculatively issues requests on a node interconnect
US6167492A (en) 1998-12-23 2000-12-26 Advanced Micro Devices, Inc. Circuit and method for maintaining order of memory access requests initiated by devices coupled to a multiprocessor system
US6256713B1 (en) * 1999-04-29 2001-07-03 International Business Machines Corporation Bus optimization with read/write coherence including ordering responsive to collisions
US6636939B1 (en) * 2000-06-29 2003-10-21 Intel Corporation Method and apparatus for processor bypass path to system memory
US6647466B2 (en) 2001-01-25 2003-11-11 Hewlett-Packard Development Company, L.P. Method and apparatus for adaptively bypassing one or more levels of a cache hierarchy
US6799217B2 (en) * 2001-06-04 2004-09-28 Fujitsu Limited Shared memory multiprocessor expansion port for multi-node systems
US7034849B1 (en) 2001-12-31 2006-04-25 Apple Computer, Inc. Method and apparatus for image blending
US7681013B1 (en) 2001-12-31 2010-03-16 Apple Inc. Method for variable length decoding using multiple configurable look-up tables
US7015921B1 (en) * 2001-12-31 2006-03-21 Apple Computer, Inc. Method and apparatus for memory access
US8055492B2 (en) * 2002-01-10 2011-11-08 International Business Machines Corporation Non-unique results in design verification by test programs
JP3791433B2 (ja) * 2002-02-27 2006-06-28 日本電気株式会社 システム、制御処理装置、およびシステム制御方法
US7103728B2 (en) * 2002-07-23 2006-09-05 Hewlett-Packard Development Company, L.P. System and method for memory migration in distributed-memory multi-processor systems
US7577816B2 (en) * 2003-08-18 2009-08-18 Cray Inc. Remote translation mechanism for a multinode system
US6895476B2 (en) * 2002-10-03 2005-05-17 Hewlett-Packard Development Company, L.P. Retry-based late race resolution mechanism for a computer system
US7024520B2 (en) * 2002-10-03 2006-04-04 Hewlett-Packard Development Company, L.P. System and method enabling efficient cache line reuse in a computer system
US7003635B2 (en) * 2002-10-03 2006-02-21 Hewlett-Packard Development Company, L.P. Generalized active inheritance consistency mechanism having linked writes
US6898676B2 (en) * 2002-10-03 2005-05-24 Hewlett-Packard Development Company, L.P. Computer system supporting both dirty-shared and non-dirty-shared data processing entities
US7000080B2 (en) * 2002-10-03 2006-02-14 Hewlett-Packard Development Company, L.P. Channel-based late race resolution mechanism for a computer system
US6892290B2 (en) * 2002-10-03 2005-05-10 Hewlett-Packard Development Company, L.P. Linked-list early race resolution mechanism
US6990559B2 (en) * 2002-10-03 2006-01-24 Hewlett-Packard Development Company, L.P. Mechanism for resolving ambiguous invalidates in a computer system
US7051163B2 (en) * 2002-10-03 2006-05-23 Hewlett-Packard Development Company, L.P. Directory structure permitting efficient write-backs in a shared memory computer system
EP1426866A1 (de) * 2002-12-06 2004-06-09 Sun Microsystems, Inc. Verfahren zur Verminderung der Speicherlatenzzeit mittels zweistufiger Spekulation
JP3764893B2 (ja) * 2003-05-30 2006-04-12 富士通株式会社 マルチプロセッサシステム
US7334110B1 (en) 2003-08-18 2008-02-19 Cray Inc. Decoupled scalar/vector computer architecture system and method
US7503048B1 (en) 2003-08-18 2009-03-10 Cray Incorporated Scheduling synchronization of programs running as streams on multiple processors
US7543133B1 (en) 2003-08-18 2009-06-02 Cray Inc. Latency tolerant distributed shared memory multiprocessor computer
US7421565B1 (en) 2003-08-18 2008-09-02 Cray Inc. Method and apparatus for indirectly addressed vector load-add -store across multi-processors
US7366873B1 (en) 2003-08-18 2008-04-29 Cray, Inc. Indirectly addressed vector load-operate-store method and apparatus
US7437521B1 (en) 2003-08-18 2008-10-14 Cray Inc. Multistream processing memory-and barrier-synchronization method and apparatus
US7735088B1 (en) 2003-08-18 2010-06-08 Cray Inc. Scheduling synchronization of programs running as streams on multiple processors
US7519771B1 (en) 2003-08-18 2009-04-14 Cray Inc. System and method for processing memory instructions using a forced order queue
US8307194B1 (en) 2003-08-18 2012-11-06 Cray Inc. Relaxed memory consistency model
US7743223B2 (en) * 2003-08-18 2010-06-22 Cray Inc. Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system
JP2005128963A (ja) * 2003-10-27 2005-05-19 Toshiba Information Systems (Japan) Corp 記憶制御装置及びｄｍａ転送が可能な制御システム
US7478769B1 (en) 2005-03-09 2009-01-20 Cray Inc. Method and apparatus for cooling electronic components
US20070186052A1 (en) * 2006-02-07 2007-08-09 International Business Machines Corporation Methods and apparatus for reducing command processing latency while maintaining coherence
US7512723B2 (en) * 2006-12-29 2009-03-31 Freescale Semiconductor, Inc. Queued interface devices, multi-core peripheral systems, and methods for sharing a peripheral in a multi-core system
JP5100176B2 (ja) * 2007-03-29 2012-12-19 株式会社東芝 マルチプロセッサシステム
US8131941B2 (en) * 2007-09-21 2012-03-06 Mips Technologies, Inc. Support for multiple coherence domains
US20090089510A1 (en) 2007-09-28 2009-04-02 Mips Technologies, Inc. Speculative read in a cache coherent microprocessor
US20090138890A1 (en) * 2007-11-21 2009-05-28 Arm Limited Contention management for a hardware transactional memory
US9513959B2 (en) * 2007-11-21 2016-12-06 Arm Limited Contention management for a hardware transactional memory
US8392663B2 (en) * 2007-12-12 2013-03-05 Mips Technologies, Inc. Coherent instruction cache utilizing cache-op execution resources
US20090248988A1 (en) * 2008-03-28 2009-10-01 Mips Technologies, Inc. Mechanism for maintaining consistency of data written by io devices
US8429353B2 (en) * 2008-05-20 2013-04-23 Oracle America, Inc. Distributed home-node hub
US8108584B2 (en) * 2008-10-15 2012-01-31 Intel Corporation Use of completer knowledge of memory region ordering requirements to modify transaction attributes
US9990287B2 (en) * 2011-12-21 2018-06-05 Intel Corporation Apparatus and method for memory-hierarchy aware producer-consumer instruction
US9196347B2 (en) * 2013-03-14 2015-11-24 International Business Machines Corporation DRAM controller for variable refresh operation timing
US10303603B2 (en) * 2017-06-13 2019-05-28 Microsoft Technology Licensing, Llc Low power multi-core coherency
US10282298B2 (en) 2017-06-13 2019-05-07 Microsoft Technology Licensing, Llc Store buffer supporting direct stores to a coherence point
KR20210123555A (ko) * 2020-04-03 2021-10-14 에스케이하이닉스 주식회사 메모리 시스템
US20230032137A1 (en) * 2021-08-02 2023-02-02 Red Hat, Inc. Efficient dirty page expiration
CN116527555B (zh) * 2023-06-20 2023-09-12 中国标准化研究院 一种跨平台数据互通一致性测试方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4473880A (en) * 1982-01-26 1984-09-25 Intel Corporation Arbitration means for controlling access to a bus shared by a number of modules
US4768148A (en) * 1986-06-27 1988-08-30 Honeywell Bull Inc. Read in process memory apparatus
DE68924306T2 (de) * 1988-06-27 1996-05-09 Digital Equipment Corp Mehrprozessorrechneranordnungen mit gemeinsamem Speicher und privaten Cache-Speichern.
EP0388574B1 (de) * 1989-03-23 1994-06-15 International Business Machines Corporation Verfahren und Vorrichtung zum Vielfachzugriff mit verteilten Warteschlangen in einem Kommunikationssystem
US5345578A (en) * 1989-06-30 1994-09-06 Digital Equipment Corporation Competitive snoopy caching for large-scale multiprocessors
CA2051209C (en) * 1990-11-30 1996-05-07 Pradeep S. Sindhu Consistency protocols for shared memory multiprocessors
US5406504A (en) * 1993-06-30 1995-04-11 Digital Equipment Multiprocessor cache examiner and coherency checker

Also Published As

Publication number Publication date
US5530933A (en) 1996-06-25
EP0669578A2 (de) 1995-08-30
EP0669578B1 (de) 2000-04-05
DE69423874T2 (de) 2000-11-16
KR100371845B1 (ko) 2003-04-03
TW260770B (de) 1995-10-21
JPH07281956A (ja) 1995-10-27
JP3640997B2 (ja) 2005-04-20
KR950033893A (ko) 1995-12-26
EP0669578A3 (de) 1995-11-15

Similar Documents

Publication Publication Date Title
DE69423874D1 (de) Verbessertes Schema zur geordneten Cachespeicherkohärenz
BR9607530A (pt) Cache de configuração rápida
DE69132186D1 (de) Cache-Speicherverwaltungsanordnung
ATE222774T1 (de) Antikörper gegen cd 18 zur verwendung gegen gehirnschlag
FI101975B (fi) Sähkösaostuksessa käytettävä kationinen mikrogeeli
DE69530776D1 (de) Zweiwege set-assoziativer cache-speicher
EE03354B1 (et) Asendatud sulfoksiidide sünteesi protsess
DE69500474D1 (de) Super-Nichtstöchiametrisches Verbrennungsverfahren
DE69515667T2 (de) Verbrennungsverfahren
DE69502873D1 (de) Wegnehmbare Stützeeinheit mit Zylinderschloss
FI98770B (fi) Hierarkkinen synkronointimenetelmä
DE69529457D1 (de) Hierarchisches synchronisierungsverfahren
DE69030072D1 (de) Schneller Durchschreib-Cache-Speicher
DE69528623D1 (de) Leitgerät
DE59208307D1 (de) Zwischenspeicher
NO971126D0 (no) Eske for kondom
DE69634464D1 (de) Cachespeicher
DE4192710T1 (de) Bremsvorrichtung für Zylinder
DE59508663D1 (de) Vorrichtung zur Temperaturkompensation
DE69634465D1 (de) Cachespeicher
DE69406402D1 (de) Zwischenspeicher
KR960006939U (ko) 침대용 브라켓
DE69423750T2 (de) Ausgleicheinheit
DE59510465D1 (de) Zylindereinheit
KR960011752A (ko) 스라이딩 캐시 박스(scb)를 장착한 조회기

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE