DE69826471D1 - Verfahren zum Herstellen von nicht selbstausgerichteten, FLOTOX-EEPROM-speicherzellen - Google Patents
Verfahren zum Herstellen von nicht selbstausgerichteten, FLOTOX-EEPROM-speicherzellenInfo
- Publication number
- DE69826471D1 DE69826471D1 DE69826471T DE69826471T DE69826471D1 DE 69826471 D1 DE69826471 D1 DE 69826471D1 DE 69826471 T DE69826471 T DE 69826471T DE 69826471 T DE69826471 T DE 69826471T DE 69826471 D1 DE69826471 D1 DE 69826471D1
- Authority
- DE
- Germany
- Prior art keywords
- flotox
- aligned
- self
- memory cells
- eeprom memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP98830612A EP0994512B1 (de) | 1998-10-15 | 1998-10-15 | Verfahren zum Herstellen von nicht selbstausgerichteten, FLOTOX-EEPROM-speicherzellen |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE69826471D1 true DE69826471D1 (de) | 2004-10-28 |
Family
ID=8236834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69826471T Expired - Fee Related DE69826471D1 (de) | 1998-10-15 | 1998-10-15 | Verfahren zum Herstellen von nicht selbstausgerichteten, FLOTOX-EEPROM-speicherzellen |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6479347B1 (de) |
| EP (1) | EP0994512B1 (de) |
| DE (1) | DE69826471D1 (de) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6369422B1 (en) * | 2001-05-01 | 2002-04-09 | Atmel Corporation | Eeprom cell with asymmetric thin window |
| KR100456541B1 (ko) * | 2002-01-04 | 2004-11-09 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조방법 |
| ITMI20022467A1 (it) * | 2002-11-20 | 2004-05-21 | St Microelectronics Srl | Processo per realizzare un transistore di selezione di byte per |
| JP2009218494A (ja) * | 2008-03-12 | 2009-09-24 | Toshiba Corp | 不揮発性半導体メモリ |
| US8462553B2 (en) * | 2009-12-29 | 2013-06-11 | Aplus Flash Technology, Inc. | Cell array for highly-scalable, byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory |
| US8933500B2 (en) | 2010-09-15 | 2015-01-13 | Aplus Flash Technology, Inc. | EEPROM-based, data-oriented combo NVM design |
| US8809148B2 (en) | 2010-09-17 | 2014-08-19 | Aplus Flash Technology, Inc. | EEPROM-based, data-oriented combo NVM design |
| US8923049B2 (en) | 2011-09-09 | 2014-12-30 | Aplus Flash Technology, Inc | 1T1b and 2T2b flash-based, data-oriented EEPROM design |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5066992A (en) * | 1989-06-23 | 1991-11-19 | Atmel Corporation | Programmable and erasable MOS memory device |
| JPH088314B2 (ja) * | 1989-10-11 | 1996-01-29 | 株式会社東芝 | 不揮発性半導体記憶装置およびその製造方法 |
| US5404037A (en) * | 1994-03-17 | 1995-04-04 | National Semiconductor Corporation | EEPROM cell with the drain diffusion region self-aligned to the tunnel oxide region |
| US5656845A (en) * | 1995-03-08 | 1997-08-12 | Atmel Corporation | EEPROM on insulator |
| US5702964A (en) * | 1995-10-17 | 1997-12-30 | Lg Semicon, Co., Ltd. | Method for forming a semiconductor device having a floating gate |
| US5861347A (en) * | 1997-07-03 | 1999-01-19 | Motorola Inc. | Method for forming a high voltage gate dielectric for use in integrated circuit |
| US6159795A (en) * | 1998-07-02 | 2000-12-12 | Advanced Micro Devices, Inc. | Low voltage junction and high voltage junction optimization for flash memory |
| US6087211A (en) * | 1998-08-12 | 2000-07-11 | National Semiconductor Corporation | Method for forming a semiconductor device having non-volatile memory cells, High-voltage transistors, and low-voltage, deep sub-micron transistors |
| WO2001047012A1 (en) * | 1999-12-21 | 2001-06-28 | Koninklijke Philips Electronics N.V. | Non-volatile memory cells and periphery |
-
1998
- 1998-10-15 EP EP98830612A patent/EP0994512B1/de not_active Expired - Lifetime
- 1998-10-15 DE DE69826471T patent/DE69826471D1/de not_active Expired - Fee Related
-
1999
- 1999-10-14 US US09/419,617 patent/US6479347B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0994512B1 (de) | 2004-09-22 |
| EP0994512A1 (de) | 2000-04-19 |
| US6479347B1 (en) | 2002-11-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8339 | Ceased/non-payment of the annual fee |