DE69823337D1 - Vorrichtung und verfahren zur rückgewinnung von puffern - Google Patents

Vorrichtung und verfahren zur rückgewinnung von puffern

Info

Publication number
DE69823337D1
DE69823337D1 DE69823337T DE69823337T DE69823337D1 DE 69823337 D1 DE69823337 D1 DE 69823337D1 DE 69823337 T DE69823337 T DE 69823337T DE 69823337 T DE69823337 T DE 69823337T DE 69823337 D1 DE69823337 D1 DE 69823337D1
Authority
DE
Germany
Prior art keywords
buffers
recovery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69823337T
Other languages
English (en)
Other versions
DE69823337T2 (de
Inventor
Bahadir Erimli
Jefferson Runaldue
Chandan Egbert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69823337D1 publication Critical patent/DE69823337D1/de
Publication of DE69823337T2 publication Critical patent/DE69823337T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9021—Plurality of buffers per packet
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/02—Standardisation; Integration
    • H04L41/0213—Standardised network management protocols, e.g. simple network management protocol [SNMP]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/255—Control mechanisms for ATM switching fabrics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3027—Output queuing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9068—Intermediate storage in different physical parts of a node or terminal in the network interface card
    • H04L49/9073—Early interruption upon arrival of a fraction of a packet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9078—Intermediate storage in different physical parts of a node or terminal using an external memory or storage device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/26—Special purpose or proprietary protocols or architectures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54575—Software application
    • H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3009—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/354—Switches specially adapted for specific applications for supporting virtual local area networks [VLAN]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/45—Arrangements for providing or supporting expansion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1316—Service observation, testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13162—Fault indication and localisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
DE69823337T 1997-02-14 1998-01-30 Vorrichtung und verfahren zur rückgewinnung von puffern Expired - Lifetime DE69823337T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US3802597P 1997-02-14 1997-02-14
US38025P 1997-02-14
US08/992,927 US6233244B1 (en) 1997-02-14 1997-12-18 Method and apparatus for reclaiming buffers
US992927 1997-12-18
PCT/US1998/001988 WO1998036536A1 (en) 1997-02-14 1998-01-30 Method and apparatus for reclaiming buffers

Publications (2)

Publication Number Publication Date
DE69823337D1 true DE69823337D1 (de) 2004-05-27
DE69823337T2 DE69823337T2 (de) 2005-05-12

Family

ID=26714755

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69823337T Expired - Lifetime DE69823337T2 (de) 1997-02-14 1998-01-30 Vorrichtung und verfahren zur rückgewinnung von puffern

Country Status (4)

Country Link
US (1) US6233244B1 (de)
EP (1) EP0960511B1 (de)
DE (1) DE69823337T2 (de)
WO (1) WO1998036536A1 (de)

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US6463032B1 (en) * 1999-01-27 2002-10-08 Advanced Micro Devices, Inc. Network switching system having overflow bypass in internal rules checker
US6546010B1 (en) * 1999-02-04 2003-04-08 Advanced Micro Devices, Inc. Bandwidth efficiency in cascaded scheme
US6515990B1 (en) * 1999-03-31 2003-02-04 Advanced Micro Devices, Inc. Dequeuing logic architecture and operation in a multiport communication switch
KR20020015691A (ko) * 1999-05-21 2002-02-28 추후보정 플릿 캐쉬 방식의 패브릭 라우터
US6597693B1 (en) * 1999-05-21 2003-07-22 Advanced Micro Devices, Inc. Common scalable queuing and dequeuing architecture and method relative to network switch data rate
US6504846B1 (en) * 1999-05-21 2003-01-07 Advanced Micro Devices, Inc. Method and apparatus for reclaiming buffers using a single buffer bit
US7031305B1 (en) * 1999-05-24 2006-04-18 Advanced Micro Devices, Inc. Apparatus and method for programmable memory access slot assignment
US6564271B2 (en) * 1999-06-09 2003-05-13 Qlogic Corporation Method and apparatus for automatically transferring I/O blocks between a host system and a host adapter
US6671274B1 (en) * 1999-06-30 2003-12-30 Cisco Technology, Inc. Link list operable to increase memory bandwidth in a transmission system
EP1065835B1 (de) * 1999-06-30 2017-01-11 Texas Instruments Incorporated Paketspeicherverwaltung (PACMAN)
DE19933130A1 (de) * 1999-07-19 2001-01-25 Giesecke & Devrient Gmbh Operandenstapelspeicher und Verfahren zum Betreiben eines Operandenstapelspeichers
US20020176430A1 (en) * 2001-01-25 2002-11-28 Sangha Onkar S. Buffer management for communication systems
US6754795B2 (en) 2001-12-21 2004-06-22 Agere Systems Inc. Methods and apparatus for forming linked list queue using chunk-based structure
US7333498B2 (en) * 2002-05-15 2008-02-19 Hewlett-Packard Development Company, L.P. Method and apparatus for separating data packets in a memory buffer
US7733888B2 (en) * 2002-06-04 2010-06-08 Alcatel-Lucent Usa Inc. Pointer allocation by prime numbers
US6823437B2 (en) * 2002-07-11 2004-11-23 International Business Machines Corporation Lazy deregistration protocol for a split socket stack
US7154886B2 (en) * 2002-07-22 2006-12-26 Qlogic Corporation Method and system for primary blade selection in a multi-module fiber channel switch
US7230929B2 (en) * 2002-07-22 2007-06-12 Qlogic, Corporation Method and system for dynamically assigning domain identification in a multi-module fibre channel switch
US7397768B1 (en) 2002-09-11 2008-07-08 Qlogic, Corporation Zone management in a multi-module fibre channel switch
US7319669B1 (en) 2002-11-22 2008-01-15 Qlogic, Corporation Method and system for controlling packet flow in networks
US7450599B2 (en) * 2003-02-08 2008-11-11 Hewlett-Packard Development Company, L.P. Apparatus and method for communicating with a network
US7646767B2 (en) * 2003-07-21 2010-01-12 Qlogic, Corporation Method and system for programmable data dependant network routing
US7234101B1 (en) 2003-08-27 2007-06-19 Qlogic, Corporation Method and system for providing data integrity in storage systems
US7219263B1 (en) 2003-10-29 2007-05-15 Qlogic, Corporation Method and system for minimizing memory corruption
US20050177660A1 (en) * 2004-02-05 2005-08-11 Rajesh Mamidwar Method and system for merged rate-smoothing buffer with burst buffer
US7930377B2 (en) 2004-04-23 2011-04-19 Qlogic, Corporation Method and system for using boot servers in networks
US7669190B2 (en) 2004-05-18 2010-02-23 Qlogic, Corporation Method and system for efficiently recording processor events in host bus adapters
US7571163B2 (en) * 2004-07-13 2009-08-04 Hewlett-Packard Development Company, L.P. Method for sorting a data structure
US7577772B2 (en) * 2004-09-08 2009-08-18 Qlogic, Corporation Method and system for optimizing DMA channel selection
US20060064531A1 (en) * 2004-09-23 2006-03-23 Alston Jerald K Method and system for optimizing data transfer in networks
US7380030B2 (en) * 2004-10-01 2008-05-27 Qlogic, Corp. Method and system for using an in-line credit extender with a host bus adapter
US7676611B2 (en) * 2004-10-01 2010-03-09 Qlogic, Corporation Method and system for processing out of orders frames
US7398335B2 (en) * 2004-11-22 2008-07-08 Qlogic, Corporation Method and system for DMA optimization in host bus adapters
US7164425B2 (en) * 2004-12-21 2007-01-16 Qlogic Corporation Method and system for high speed network application
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US7742408B2 (en) * 2006-08-04 2010-06-22 Fujitsu Limited System and method for filtering packets in a switching environment
US7720802B2 (en) * 2007-01-03 2010-05-18 International Business Machines Corporation Reclaiming resident buffers when a reclaim threshold has been exceeded by swapping the oldest in use buffer and a new buffer, and referencing the new buffer via an updated set of read and write pointers
US20090222613A1 (en) * 2008-02-29 2009-09-03 Kabushiki Kaisha Toshiba Information processing apparatus and nonvolatile semiconductor memory drive
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US8364930B2 (en) * 2008-03-07 2013-01-29 Kabushiki Kaisha Toshiba Information processing apparatus and storage drive adapted to perform fault analysis by maintenance of tracing information
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Also Published As

Publication number Publication date
WO1998036536A1 (en) 1998-08-20
DE69823337T2 (de) 2005-05-12
EP0960511A1 (de) 1999-12-01
EP0960511B1 (de) 2004-04-21
US6233244B1 (en) 2001-05-15

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Legal Events

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8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC. MAPLES CORPORATE SERVICES, KY