DE69818535D1 - Gegen unbefugte Handhabung gesicherte integrierte Schaltung - Google Patents

Gegen unbefugte Handhabung gesicherte integrierte Schaltung

Info

Publication number
DE69818535D1
DE69818535D1 DE69818535T DE69818535T DE69818535D1 DE 69818535 D1 DE69818535 D1 DE 69818535D1 DE 69818535 T DE69818535 T DE 69818535T DE 69818535 T DE69818535 T DE 69818535T DE 69818535 D1 DE69818535 D1 DE 69818535D1
Authority
DE
Germany
Prior art keywords
integrated circuit
secured against
against unauthorized
circuit secured
unauthorized handling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69818535T
Other languages
English (en)
Other versions
DE69818535T2 (de
Inventor
Brant Candelore
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arris Technology Inc
Original Assignee
Arris Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arris Technology Inc filed Critical Arris Technology Inc
Publication of DE69818535D1 publication Critical patent/DE69818535D1/de
Application granted granted Critical
Publication of DE69818535T2 publication Critical patent/DE69818535T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/86—Secure or tamper-resistant housings
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2143—Clearing memory, e.g. to prevent the data from being stolen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/922—Active solid-state devices, e.g. transistors, solid-state diodes with means to prevent inspection of or tampering with an integrated circuit, e.g. "smart card", anti-tamper

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Storage Device Security (AREA)
  • Credit Cards Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69818535T 1997-02-24 1998-02-21 Gegen unbefugte Handhabung gesicherte integrierte Schaltung Expired - Fee Related DE69818535T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US806530 1997-02-24
US08/806,530 US5880523A (en) 1997-02-24 1997-02-24 Anti-tamper integrated circuit

Publications (2)

Publication Number Publication Date
DE69818535D1 true DE69818535D1 (de) 2003-11-06
DE69818535T2 DE69818535T2 (de) 2004-08-05

Family

ID=25194253

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69818535T Expired - Fee Related DE69818535T2 (de) 1997-02-24 1998-02-21 Gegen unbefugte Handhabung gesicherte integrierte Schaltung

Country Status (9)

Country Link
US (1) US5880523A (de)
EP (1) EP0860881B1 (de)
JP (1) JPH10301858A (de)
KR (1) KR19980071652A (de)
CN (1) CN1202448C (de)
CA (1) CA2230009C (de)
DE (1) DE69818535T2 (de)
ES (1) ES2208984T3 (de)
TW (1) TW375766B (de)

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US7565596B2 (en) * 2005-09-09 2009-07-21 Searete Llc Data recovery systems
US7519980B2 (en) * 2005-05-09 2009-04-14 Searete Llc Fluid mediated disk activation and deactivation mechanisms
US8462605B2 (en) 2005-05-09 2013-06-11 The Invention Science Fund I, Llc Method of manufacturing a limited use data storing device
US7668069B2 (en) * 2005-05-09 2010-02-23 Searete Llc Limited use memory device with associated information
US7668068B2 (en) * 2005-06-09 2010-02-23 Searete Llc Rotation responsive disk activation and deactivation mechanisms
US7694316B2 (en) * 2005-05-09 2010-04-06 The Invention Science Fund I, Llc Fluid mediated disk activation and deactivation mechanisms
US8121016B2 (en) * 2005-05-09 2012-02-21 The Invention Science Fund I, Llc Rotation responsive disk activation and deactivation mechanisms
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US8159925B2 (en) * 2005-08-05 2012-04-17 The Invention Science Fund I, Llc Limited use memory device with associated information
US7748012B2 (en) * 2005-05-09 2010-06-29 Searete Llc Method of manufacturing a limited use data storing device
US7770028B2 (en) * 2005-09-09 2010-08-03 Invention Science Fund 1, Llc Limited use data storing device
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US7907486B2 (en) * 2006-06-20 2011-03-15 The Invention Science Fund I, Llc Rotation responsive disk activation and deactivation mechanisms
US8218262B2 (en) 2005-05-09 2012-07-10 The Invention Science Fund I, Llc Method of manufacturing a limited use data storing device including structured data and primary and secondary read-support information
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US8432777B2 (en) * 2006-06-19 2013-04-30 The Invention Science Fund I, Llc Method and system for fluid mediated disk activation and deactivation
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Also Published As

Publication number Publication date
EP0860881A3 (de) 1999-08-18
EP0860881B1 (de) 2003-10-01
KR19980071652A (ko) 1998-10-26
CA2230009C (en) 2005-05-03
CN1197968A (zh) 1998-11-04
CA2230009A1 (en) 1998-08-24
CN1202448C (zh) 2005-05-18
JPH10301858A (ja) 1998-11-13
DE69818535T2 (de) 2004-08-05
US5880523A (en) 1999-03-09
ES2208984T3 (es) 2004-06-16
EP0860881A2 (de) 1998-08-26
TW375766B (en) 1999-12-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee