DE69811474D1 - Rechnerarchitektur zur aufschiebung von exceptions statischer spekulativer befehle - Google Patents
Rechnerarchitektur zur aufschiebung von exceptions statischer spekulativer befehleInfo
- Publication number
- DE69811474D1 DE69811474D1 DE69811474T DE69811474T DE69811474D1 DE 69811474 D1 DE69811474 D1 DE 69811474D1 DE 69811474 T DE69811474 T DE 69811474T DE 69811474 T DE69811474 T DE 69811474T DE 69811474 D1 DE69811474 D1 DE 69811474D1
- Authority
- DE
- Germany
- Prior art keywords
- hardware
- stored information
- exceptions
- speculative
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000003068 static effect Effects 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/949,295 US5915117A (en) | 1997-10-13 | 1997-10-13 | Computer architecture for the deferral of exceptions on speculative instructions |
US949295 | 1997-10-13 | ||
PCT/US1998/021454 WO1999019794A1 (en) | 1997-10-13 | 1998-10-09 | Computer architecture for the deferral of exceptions on speculative instructions |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69811474D1 true DE69811474D1 (de) | 2003-03-27 |
DE69811474T2 DE69811474T2 (de) | 2004-01-08 |
Family
ID=25488867
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69811474T Expired - Fee Related DE69811474T2 (de) | 1997-10-13 | 1998-10-09 | Rechnerarchitektur zur aufschiebung von exceptions statischer spekulativer befehle |
Country Status (6)
Country | Link |
---|---|
US (1) | US5915117A (de) |
EP (1) | EP0951672B1 (de) |
AT (1) | ATE232998T1 (de) |
AU (1) | AU758574B2 (de) |
DE (1) | DE69811474T2 (de) |
WO (1) | WO1999019794A1 (de) |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6505296B2 (en) | 1997-10-13 | 2003-01-07 | Hewlett-Packard Company | Emulated branch effected by trampoline mechanism |
US6173248B1 (en) * | 1998-02-09 | 2001-01-09 | Hewlett-Packard Company | Method and apparatus for handling masked exceptions in an instruction interpreter |
US6260190B1 (en) * | 1998-08-11 | 2001-07-10 | Hewlett-Packard Company | Unified compiler framework for control and data speculation with recovery code |
US6301705B1 (en) * | 1998-10-01 | 2001-10-09 | Institute For The Development Of Emerging Architectures, L.L.C. | System and method for deferring exceptions generated during speculative execution |
US6519694B2 (en) * | 1999-02-04 | 2003-02-11 | Sun Microsystems, Inc. | System for handling load errors having symbolic entity generator to generate symbolic entity and ALU to propagate the symbolic entity |
US7761857B1 (en) * | 1999-10-13 | 2010-07-20 | Robert Bedichek | Method for switching between interpretation and dynamic translation in a processor system based upon code sequence execution counts |
US6542984B1 (en) * | 2000-01-03 | 2003-04-01 | Advanced Micro Devices, Inc. | Scheduler capable of issuing and reissuing dependency chains |
US6622235B1 (en) | 2000-01-03 | 2003-09-16 | Advanced Micro Devices, Inc. | Scheduler which retries load/store hit situations |
US6564315B1 (en) * | 2000-01-03 | 2003-05-13 | Advanced Micro Devices, Inc. | Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction |
US6594821B1 (en) | 2000-03-30 | 2003-07-15 | Transmeta Corporation | Translation consistency checking for modified target instructions by comparing to original copy |
US6631460B1 (en) | 2000-04-27 | 2003-10-07 | Institute For The Development Of Emerging Architectures, L.L.C. | Advanced load address table entry invalidation based on register address wraparound |
US7188232B1 (en) * | 2000-05-03 | 2007-03-06 | Choquette Jack H | Pipelined processing with commit speculation staging buffer and load/store centric exception handling |
US6615343B1 (en) * | 2000-06-22 | 2003-09-02 | Sun Microsystems, Inc. | Mechanism for delivering precise exceptions in an out-of-order processor with speculative execution |
US6895527B1 (en) * | 2000-09-30 | 2005-05-17 | Intel Corporation | Error recovery for speculative memory accesses |
US6829700B2 (en) * | 2000-12-29 | 2004-12-07 | Stmicroelectronics, Inc. | Circuit and method for supporting misaligned accesses in the presence of speculative load instructions |
US20020199179A1 (en) * | 2001-06-21 | 2002-12-26 | Lavery Daniel M. | Method and apparatus for compiler-generated triggering of auxiliary codes |
US7240186B2 (en) * | 2001-07-16 | 2007-07-03 | Hewlett-Packard Development Company, L.P. | System and method to avoid resource contention in the presence of exceptions |
KR20040058228A (ko) * | 2001-10-25 | 2004-07-03 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | 낮은 오버헤드의 예외 체킹 |
US6941449B2 (en) * | 2002-03-04 | 2005-09-06 | Hewlett-Packard Development Company, L.P. | Method and apparatus for performing critical tasks using speculative operations |
US7051238B2 (en) * | 2002-07-30 | 2006-05-23 | Hewlett-Packard Development Company, L.P. | Method and system for using machine-architecture support to distinguish function and routine return values |
US20040123081A1 (en) * | 2002-12-20 | 2004-06-24 | Allan Knies | Mechanism to increase performance of control speculation |
US7310723B1 (en) * | 2003-04-02 | 2007-12-18 | Transmeta Corporation | Methods and systems employing a flag for deferring exception handling to a commit or rollback point |
US7321964B2 (en) * | 2003-07-08 | 2008-01-22 | Advanced Micro Devices, Inc. | Store-to-load forwarding buffer using indexed lookup |
US20050283770A1 (en) * | 2004-06-18 | 2005-12-22 | Karp Alan H | Detecting memory address bounds violations |
US7194604B2 (en) * | 2004-08-26 | 2007-03-20 | International Business Machines Corporation | Address generation interlock resolution under runahead execution |
US20060181949A1 (en) * | 2004-12-31 | 2006-08-17 | Kini M V | Operating system-independent memory power management |
US8413162B1 (en) | 2005-06-28 | 2013-04-02 | Guillermo J. Rozas | Multi-threading based on rollback |
US9772853B1 (en) * | 2007-09-17 | 2017-09-26 | Rocket Software, Inc | Dispatching a unit of work to a specialty engine or a general processor and exception handling including continuing execution until reaching a defined exit point or restarting execution at a predefined retry point using a different engine or processor |
US8458684B2 (en) * | 2009-08-19 | 2013-06-04 | International Business Machines Corporation | Insertion of operation-and-indicate instructions for optimized SIMD code |
US20110047358A1 (en) * | 2009-08-19 | 2011-02-24 | International Business Machines Corporation | In-Data Path Tracking of Floating Point Exceptions and Store-Based Exception Indication |
US8966230B2 (en) * | 2009-09-30 | 2015-02-24 | Intel Corporation | Dynamic selection of execution stage |
WO2012107800A1 (en) * | 2011-02-11 | 2012-08-16 | Freescale Semiconductor, Inc. | Integrated circuit devices and methods for scheduling and executing a restricted load operation |
US11176055B1 (en) | 2019-08-06 | 2021-11-16 | Marvell Asia Pte, Ltd. | Managing potential faults for speculative page table access |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5201043A (en) * | 1989-04-05 | 1993-04-06 | Intel Corporation | System using both a supervisor level control bit and a user level control bit to enable/disable memory reference alignment checking |
US5278985A (en) * | 1990-10-31 | 1994-01-11 | Hewlett-Packard Company | Software method for implementing dismissible instructions on a computer |
US5692169A (en) * | 1990-12-14 | 1997-11-25 | Hewlett Packard Company | Method and system for deferring exceptions generated during speculative execution |
US5778219A (en) * | 1990-12-14 | 1998-07-07 | Hewlett-Packard Company | Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations |
US5438677A (en) * | 1992-08-17 | 1995-08-01 | Intel Corporation | Mutual exclusion for computer system |
US5634023A (en) * | 1994-07-01 | 1997-05-27 | Digital Equipment Corporation | Software mechanism for accurately handling exceptions generated by speculatively scheduled instructions |
US5666508A (en) * | 1995-06-07 | 1997-09-09 | Texas Instruments Incorporated | Four state two bit recoded alignment fault state circuit for microprocessor address misalignment fault generation |
WO1998006038A1 (en) * | 1996-08-07 | 1998-02-12 | Sun Microsystems, Inc. | Architectural support for software pipelining of loops |
-
1997
- 1997-10-13 US US08/949,295 patent/US5915117A/en not_active Expired - Lifetime
-
1998
- 1998-10-09 AT AT98952242T patent/ATE232998T1/de not_active IP Right Cessation
- 1998-10-09 DE DE69811474T patent/DE69811474T2/de not_active Expired - Fee Related
- 1998-10-09 WO PCT/US1998/021454 patent/WO1999019794A1/en active IP Right Grant
- 1998-10-09 EP EP98952242A patent/EP0951672B1/de not_active Expired - Lifetime
- 1998-10-09 AU AU97990/98A patent/AU758574B2/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
WO1999019794A1 (en) | 1999-04-22 |
DE69811474T2 (de) | 2004-01-08 |
EP0951672A1 (de) | 1999-10-27 |
EP0951672B1 (de) | 2003-02-19 |
ATE232998T1 (de) | 2003-03-15 |
US5915117A (en) | 1999-06-22 |
AU758574B2 (en) | 2003-03-27 |
AU9799098A (en) | 1999-05-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |