DE69802605D1 - Im System programmierbarer Verbindungsschaltkreis - Google Patents

Im System programmierbarer Verbindungsschaltkreis

Info

Publication number
DE69802605D1
DE69802605D1 DE69802605T DE69802605T DE69802605D1 DE 69802605 D1 DE69802605 D1 DE 69802605D1 DE 69802605 T DE69802605 T DE 69802605T DE 69802605 T DE69802605 T DE 69802605T DE 69802605 D1 DE69802605 D1 DE 69802605D1
Authority
DE
Germany
Prior art keywords
link circuit
circuit programmable
programmable
link
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69802605T
Other languages
English (en)
Other versions
DE69802605T2 (de
Inventor
Kopec, Jr
Cheng-Yuan Michael Wang
Jerome Connelly Farmer
Cyrus Y Tsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lattice Semiconductor Corp
Original Assignee
Lattice Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lattice Semiconductor Corp filed Critical Lattice Semiconductor Corp
Publication of DE69802605D1 publication Critical patent/DE69802605D1/de
Application granted granted Critical
Publication of DE69802605T2 publication Critical patent/DE69802605T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE69802605T 1997-04-07 1998-03-30 Im System programmierbarer Verbindungsschaltkreis Expired - Fee Related DE69802605T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/838,487 US6034541A (en) 1997-04-07 1997-04-07 In-system programmable interconnect circuit

Publications (2)

Publication Number Publication Date
DE69802605D1 true DE69802605D1 (de) 2002-01-10
DE69802605T2 DE69802605T2 (de) 2002-07-25

Family

ID=25277204

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69802605T Expired - Fee Related DE69802605T2 (de) 1997-04-07 1998-03-30 Im System programmierbarer Verbindungsschaltkreis

Country Status (4)

Country Link
US (1) US6034541A (de)
EP (1) EP0871292B1 (de)
JP (1) JPH10341154A (de)
DE (1) DE69802605T2 (de)

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US6055659A (en) * 1999-02-26 2000-04-25 Texas Instruments Incorporated Boundary scan with latching output buffer and weak input buffer
US6255847B1 (en) 1998-05-21 2001-07-03 Lattice Semiconductor Corporation Programmable logic device
US6229336B1 (en) * 1998-05-21 2001-05-08 Lattice Semiconductor Corporation Programmable integrated circuit device with slew control and skew control
US6876960B1 (en) * 1999-09-27 2005-04-05 The Board Of Trustees Of The University Of Illinois Method and apparatus for remotely assembling a physical system
US6724220B1 (en) 2000-10-26 2004-04-20 Cyress Semiconductor Corporation Programmable microcontroller architecture (mixed analog/digital)
US8176296B2 (en) 2000-10-26 2012-05-08 Cypress Semiconductor Corporation Programmable microcontroller architecture
US6590417B1 (en) * 2001-04-03 2003-07-08 Cypress Semiconductor Corporation Cascadable bus based crossbar switch in a programmable logic device
US6452417B1 (en) * 2001-04-12 2002-09-17 Cypress Semiconductor Corporation I/O cell architecture for CPLDs
US6586966B1 (en) * 2001-09-13 2003-07-01 Altera Corporation Data latch with low-power bypass mode
US7406674B1 (en) 2001-10-24 2008-07-29 Cypress Semiconductor Corporation Method and apparatus for generating microcontroller configuration information
US8042093B1 (en) 2001-11-15 2011-10-18 Cypress Semiconductor Corporation System providing automatic source code generation for personalization and parameterization of user modules
US6650141B2 (en) * 2001-12-14 2003-11-18 Lattice Semiconductor Corporation High speed interface for a programmable interconnect circuit
US6653861B1 (en) * 2001-12-14 2003-11-25 Lattice Semiconductor Corporation Multi-level routing structure for a programmable interconnect circuit
US6661254B1 (en) 2001-12-14 2003-12-09 Lattice Semiconductor Corporation Programmable interconnect circuit with a phase-locked loop
US7154298B1 (en) 2001-12-14 2006-12-26 Lattice Semiconductor Corporation Block-oriented architecture for a programmable interconnect circuit
US6703860B1 (en) 2001-12-14 2004-03-09 Lattice Semiconductor Corporation I/O block for a programmable interconnect circuit
US6759869B1 (en) * 2002-06-05 2004-07-06 Xilinx, Inc. Large crossbar switch implemented in FPGA
US6922078B1 (en) * 2003-05-01 2005-07-26 Lattice Semiconductor Corporation Programmable logic device with enhanced wide and deep logic capability
US7521960B2 (en) * 2003-07-31 2009-04-21 Actel Corporation Integrated circuit including programmable logic and external-device chip-enable override control
US7170315B2 (en) * 2003-07-31 2007-01-30 Actel Corporation Programmable system on a chip
US7190974B2 (en) * 2004-03-26 2007-03-13 Broadcom Corporation Shared antenna control
US7138824B1 (en) * 2004-05-10 2006-11-21 Actel Corporation Integrated multi-function analog circuit including voltage, current, and temperature monitor and gate-driver circuit blocks
US7099189B1 (en) 2004-10-05 2006-08-29 Actel Corporation SRAM cell controlled by non-volatile memory cell
US7487571B2 (en) * 2004-11-29 2009-02-10 Fong Luk Control adjustable device configurations to induce parameter variations to control parameter skews
US7116181B2 (en) * 2004-12-21 2006-10-03 Actel Corporation Voltage- and temperature-compensated RC oscillator circuit
US7119398B1 (en) * 2004-12-22 2006-10-10 Actel Corporation Power-up and power-down circuit for system-on-a-chip integrated circuit
US7446378B2 (en) * 2004-12-29 2008-11-04 Actel Corporation ESD protection structure for I/O pad subject to both positive and negative voltages
WO2006072142A1 (en) * 2005-01-06 2006-07-13 Justin Martin Spangaro A reprogrammable integrated circuit
JP4830371B2 (ja) * 2005-06-30 2011-12-07 セイコーエプソン株式会社 集積回路装置及び電子機器
US7764278B2 (en) * 2005-06-30 2010-07-27 Seiko Epson Corporation Integrated circuit device and electronic instrument
JP4010335B2 (ja) * 2005-06-30 2007-11-21 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4151688B2 (ja) * 2005-06-30 2008-09-17 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4345725B2 (ja) * 2005-06-30 2009-10-14 セイコーエプソン株式会社 表示装置及び電子機器
JP4010334B2 (ja) * 2005-06-30 2007-11-21 セイコーエプソン株式会社 集積回路装置及び電子機器
KR100826695B1 (ko) 2005-06-30 2008-04-30 세이코 엡슨 가부시키가이샤 집적 회로 장치 및 전자 기기
US7593270B2 (en) 2005-06-30 2009-09-22 Seiko Epson Corporation Integrated circuit device and electronic instrument
US20070016700A1 (en) * 2005-06-30 2007-01-18 Seiko Epson Corporation Integrated circuit device and electronic instrument
KR100850614B1 (ko) * 2005-06-30 2008-08-05 세이코 엡슨 가부시키가이샤 집적 회로 장치 및 전자 기기
JP2007012869A (ja) 2005-06-30 2007-01-18 Seiko Epson Corp 集積回路装置及び電子機器
JP4010333B2 (ja) * 2005-06-30 2007-11-21 セイコーエプソン株式会社 集積回路装置及び電子機器
US20070001974A1 (en) * 2005-06-30 2007-01-04 Seiko Epson Corporation Integrated circuit device and electronic instrument
JP4661401B2 (ja) * 2005-06-30 2011-03-30 セイコーエプソン株式会社 集積回路装置及び電子機器
KR100828792B1 (ko) * 2005-06-30 2008-05-09 세이코 엡슨 가부시키가이샤 집적 회로 장치 및 전자 기기
JP4186970B2 (ja) * 2005-06-30 2008-11-26 セイコーエプソン株式会社 集積回路装置及び電子機器
JP2007012925A (ja) * 2005-06-30 2007-01-18 Seiko Epson Corp 集積回路装置及び電子機器
US7564734B2 (en) * 2005-06-30 2009-07-21 Seiko Epson Corporation Integrated circuit device and electronic instrument
US7567479B2 (en) * 2005-06-30 2009-07-28 Seiko Epson Corporation Integrated circuit device and electronic instrument
US20070001975A1 (en) * 2005-06-30 2007-01-04 Seiko Epson Corporation Integrated circuit device and electronic instrument
JP4661400B2 (ja) * 2005-06-30 2011-03-30 セイコーエプソン株式会社 集積回路装置及び電子機器
US20070001970A1 (en) * 2005-06-30 2007-01-04 Seiko Epson Corporation Integrated circuit device and electronic instrument
US20070001984A1 (en) * 2005-06-30 2007-01-04 Seiko Epson Corporation Integrated circuit device and electronic instrument
JP4010332B2 (ja) * 2005-06-30 2007-11-21 セイコーエプソン株式会社 集積回路装置及び電子機器
US7561478B2 (en) 2005-06-30 2009-07-14 Seiko Epson Corporation Integrated circuit device and electronic instrument
JP4010336B2 (ja) * 2005-06-30 2007-11-21 セイコーエプソン株式会社 集積回路装置及び電子機器
US7755587B2 (en) * 2005-06-30 2010-07-13 Seiko Epson Corporation Integrated circuit device and electronic instrument
JP4158788B2 (ja) * 2005-06-30 2008-10-01 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4665677B2 (ja) 2005-09-09 2011-04-06 セイコーエプソン株式会社 集積回路装置及び電子機器
US7345508B1 (en) * 2006-01-24 2008-03-18 Xilinx, Inc. Programmable logic device having a programmable selector circuit
JP4586739B2 (ja) * 2006-02-10 2010-11-24 セイコーエプソン株式会社 半導体集積回路及び電子機器
US7330051B1 (en) 2006-02-14 2008-02-12 Altera Corporation Innovated technique to reduce memory interface write mode SSN in FPGA
US8813021B1 (en) 2006-02-16 2014-08-19 Cypress Semiconductor Corporation Global resource conflict management for an embedded application design
US8417867B2 (en) * 2010-11-17 2013-04-09 Xilinx, Inc. Multichip module for communications
US9210486B2 (en) 2013-03-01 2015-12-08 Qualcomm Incorporated Switching fabric for embedded reconfigurable computing

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212652A (en) * 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
US5237218A (en) * 1991-05-03 1993-08-17 Lattice Semiconductor Corporation Structure and method for multiplexing pins for in-system programming
EP0584910B1 (de) * 1992-08-03 1996-09-04 Advanced Micro Devices, Inc. Programmierbare logische Vorrichtung
US5561773A (en) * 1993-04-30 1996-10-01 Unisys Corporation Programmable, multi-purpose virtual pin multiplier
US5404055A (en) * 1993-09-01 1995-04-04 Lattice Semiconductor Corporation Input routing pool

Also Published As

Publication number Publication date
EP0871292B1 (de) 2001-11-28
JPH10341154A (ja) 1998-12-22
US6034541A (en) 2000-03-07
DE69802605T2 (de) 2002-07-25
EP0871292A1 (de) 1998-10-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee