DE69802135D1 - Logische Vorrichtung - Google Patents

Logische Vorrichtung

Info

Publication number
DE69802135D1
DE69802135D1 DE69802135T DE69802135T DE69802135D1 DE 69802135 D1 DE69802135 D1 DE 69802135D1 DE 69802135 T DE69802135 T DE 69802135T DE 69802135 T DE69802135 T DE 69802135T DE 69802135 D1 DE69802135 D1 DE 69802135D1
Authority
DE
Germany
Prior art keywords
output
differential
type
logical device
symmetrical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69802135T
Other languages
English (en)
Other versions
DE69802135T2 (de
Inventor
Andrew James Pickering
Giuseppe Surace
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Ltd
Original Assignee
Phoenix VLSI Consultants Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix VLSI Consultants Ltd filed Critical Phoenix VLSI Consultants Ltd
Application granted granted Critical
Publication of DE69802135D1 publication Critical patent/DE69802135D1/de
Publication of DE69802135T2 publication Critical patent/DE69802135T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Debugging And Monitoring (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Analogue/Digital Conversion (AREA)
DE69802135T 1997-04-30 1998-04-30 Logische Vorrichtung Expired - Lifetime DE69802135T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB9708865.2A GB9708865D0 (en) 1997-04-30 1997-04-30 ECL-CMOS converter

Publications (2)

Publication Number Publication Date
DE69802135D1 true DE69802135D1 (de) 2001-11-29
DE69802135T2 DE69802135T2 (de) 2002-07-04

Family

ID=10811653

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69802135T Expired - Lifetime DE69802135T2 (de) 1997-04-30 1998-04-30 Logische Vorrichtung

Country Status (5)

Country Link
US (1) US6121793A (de)
EP (1) EP0875996B1 (de)
AT (1) ATE207676T1 (de)
DE (1) DE69802135T2 (de)
GB (1) GB9708865D0 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100513710B1 (ko) * 1999-05-25 2005-09-07 삼성전자주식회사 Ｃｄｍａ 통신시스템의 코드동기 취득방법 및 그 장치
US6424194B1 (en) 1999-06-28 2002-07-23 Broadcom Corporation Current-controlled CMOS logic family
US6795493B1 (en) 1999-11-23 2004-09-21 Realtek Semiconductor Corp. Circuit for a transceiver output port of a local area networking device
US7075977B2 (en) 1999-11-23 2006-07-11 Realtek Semiconductor Corp. Circuit for a transceiver output port of a local area networking device
GB0413152D0 (en) * 2004-06-14 2004-07-14 Texas Instruments Ltd Duty cycle controlled CML-CMOS converter
JP2006054886A (ja) * 2004-08-09 2006-02-23 Samsung Electronics Co Ltd ロー漏洩電流を持つレベルシフタ
KR100587689B1 (ko) * 2004-08-09 2006-06-08 삼성전자주식회사 반도체 장치에 적합한 레벨 시프트 회로
JP2006279203A (ja) * 2005-03-28 2006-10-12 Fujitsu Ltd レベル変換回路
KR20130130478A (ko) * 2012-05-22 2013-12-02 삼성전자주식회사 입력 버퍼

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0618308B2 (ja) * 1985-04-08 1994-03-09 ソニー株式会社 平衡型差動増幅器
JPH07118642B2 (ja) * 1986-01-08 1995-12-18 株式会社東芝 レベル変換回路
US4806796A (en) * 1988-03-28 1989-02-21 Motorola, Inc. Active load for emitter coupled logic gate
US5148061A (en) * 1991-02-27 1992-09-15 Motorola, Inc. ECL to CMOS translation and latch logic circuit
US5149992A (en) * 1991-04-30 1992-09-22 The State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University MOS folded source-coupled logic
US5264745A (en) * 1992-08-28 1993-11-23 Advanced Micro Devices, Inc. Recovering phase and data from distorted duty cycles caused by ECL-to-CMOS translator
US5317214A (en) * 1993-03-09 1994-05-31 Raytheon Company Interface circuit having differential signal common mode shifting means
TW307064B (de) * 1993-09-08 1997-06-01 Advanced Micro Devices Inc
JP3149759B2 (ja) * 1995-11-17 2001-03-26 日本電気株式会社 ラッチ回路
US5818269A (en) * 1997-04-01 1998-10-06 National Semiconductor Corporation Differential current mode driver

Also Published As

Publication number Publication date
EP0875996A1 (de) 1998-11-04
DE69802135T2 (de) 2002-07-04
EP0875996B1 (de) 2001-10-24
ATE207676T1 (de) 2001-11-15
GB9708865D0 (en) 1997-06-25
US6121793A (en) 2000-09-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: TEXAS INSTRUMENTS LTD., NORTHAMPTON BUSINESS PARK,