DE69736105D1 - Hierarchische durchsuchlogik für ungeordnete lade/speicherausführungssteuerung - Google Patents
Hierarchische durchsuchlogik für ungeordnete lade/speicherausführungssteuerungInfo
- Publication number
- DE69736105D1 DE69736105D1 DE69736105T DE69736105T DE69736105D1 DE 69736105 D1 DE69736105 D1 DE 69736105D1 DE 69736105 T DE69736105 T DE 69736105T DE 69736105 T DE69736105 T DE 69736105T DE 69736105 D1 DE69736105 D1 DE 69736105D1
- Authority
- DE
- Germany
- Prior art keywords
- unlawful
- loading
- execution control
- hierarchical search
- memory execution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/592,209 US5754812A (en) | 1995-10-06 | 1996-01-26 | Out-of-order load/store execution control |
US592209 | 1996-01-26 | ||
US740119 | 1996-10-23 | ||
US08/740,119 US5835747A (en) | 1996-01-26 | 1996-10-23 | Hierarchical scan logic for out-of-order load/store execution control |
PCT/US1997/000294 WO1997027538A1 (en) | 1996-01-26 | 1997-01-22 | Hierarchical scan logic for out-of-order load/store execution control |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69736105D1 true DE69736105D1 (de) | 2006-07-27 |
DE69736105T2 DE69736105T2 (de) | 2007-01-11 |
Family
ID=27081403
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69736105T Expired - Lifetime DE69736105T2 (de) | 1996-01-26 | 1997-01-22 | Hierarchische durchsuchlogik für ungeordnete lade/speicherausführungssteuerung |
Country Status (6)
Country | Link |
---|---|
US (1) | US5835747A (de) |
EP (1) | EP0876646B1 (de) |
JP (1) | JP3681761B2 (de) |
AU (1) | AU1530997A (de) |
DE (1) | DE69736105T2 (de) |
WO (1) | WO1997027538A1 (de) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5987595A (en) * | 1997-11-25 | 1999-11-16 | Intel Corporation | Method and apparatus for predicting when load instructions can be executed out-of order |
US6192464B1 (en) * | 1997-12-31 | 2001-02-20 | Intel Corporation | Method and apparatus for decoding one or more instructions after renaming destination registers |
WO2000011548A1 (en) * | 1998-08-24 | 2000-03-02 | Advanced Micro Devices, Inc. | Mechanism for load block on store address generation and universal dependency vector |
US6212623B1 (en) | 1998-08-24 | 2001-04-03 | Advanced Micro Devices, Inc. | Universal dependency vector/queue entry |
US6122727A (en) * | 1998-08-24 | 2000-09-19 | Advanced Micro Devices, Inc. | Symmetrical instructions queue for high clock frequency scheduling |
US6212622B1 (en) | 1998-08-24 | 2001-04-03 | Advanced Micro Devices, Inc. | Mechanism for load block on store address generation |
US6141747A (en) * | 1998-09-22 | 2000-10-31 | Advanced Micro Devices, Inc. | System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word |
US6223259B1 (en) * | 1998-10-30 | 2001-04-24 | Telefonaktiebolaget Lm Ericsson (Publ) | Reducing read cycle of memory read request for data to be partially modified by a pending write request |
US6167492A (en) | 1998-12-23 | 2000-12-26 | Advanced Micro Devices, Inc. | Circuit and method for maintaining order of memory access requests initiated by devices coupled to a multiprocessor system |
US6304955B1 (en) * | 1998-12-30 | 2001-10-16 | Intel Corporation | Method and apparatus for performing latency based hazard detection |
EP1050806A1 (de) * | 1999-05-03 | 2000-11-08 | STMicroelectronics SA | Speicheradressenvergleich |
US6523109B1 (en) | 1999-10-25 | 2003-02-18 | Advanced Micro Devices, Inc. | Store queue multimatch detection |
US6481251B1 (en) | 1999-10-25 | 2002-11-19 | Advanced Micro Devices, Inc. | Store queue number assignment and tracking |
US6622237B1 (en) | 2000-01-03 | 2003-09-16 | Advanced Micro Devices, Inc. | Store to load forward predictor training using delta tag |
US6694424B1 (en) | 2000-01-03 | 2004-02-17 | Advanced Micro Devices, Inc. | Store load forward predictor training |
US6622235B1 (en) | 2000-01-03 | 2003-09-16 | Advanced Micro Devices, Inc. | Scheduler which retries load/store hit situations |
US6542984B1 (en) | 2000-01-03 | 2003-04-01 | Advanced Micro Devices, Inc. | Scheduler capable of issuing and reissuing dependency chains |
US6651161B1 (en) * | 2000-01-03 | 2003-11-18 | Advanced Micro Devices, Inc. | Store load forward predictor untraining |
US6564315B1 (en) | 2000-01-03 | 2003-05-13 | Advanced Micro Devices, Inc. | Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction |
DE10110578B4 (de) * | 2000-03-29 | 2004-06-03 | International Business Machines Corporation | Hierarchisches Prioritätsfilter mit integrierter Serialisierung |
US6662293B1 (en) * | 2000-05-23 | 2003-12-09 | Sun Microsystems, Inc. | Instruction dependency scoreboard with a hierarchical structure |
US6857060B2 (en) | 2001-03-30 | 2005-02-15 | Intel Corporation | System, apparatus and method for prioritizing instructions and eliminating useless instructions |
US6963961B1 (en) * | 2001-07-09 | 2005-11-08 | Lsi Logic Corporation | Increasing DSP efficiency by independent issuance of store address and data |
US6803786B1 (en) | 2003-03-11 | 2004-10-12 | Xilinx, Inc. | Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks |
US7321964B2 (en) * | 2003-07-08 | 2008-01-22 | Advanced Micro Devices, Inc. | Store-to-load forwarding buffer using indexed lookup |
US7376817B2 (en) * | 2005-08-10 | 2008-05-20 | P.A. Semi, Inc. | Partial load/store forward prediction |
US9128725B2 (en) | 2012-05-04 | 2015-09-08 | Apple Inc. | Load-store dependency predictor content management |
US9600289B2 (en) | 2012-05-30 | 2017-03-21 | Apple Inc. | Load-store dependency predictor PC hashing |
US9710268B2 (en) | 2014-04-29 | 2017-07-18 | Apple Inc. | Reducing latency for pointer chasing loads |
US10514925B1 (en) | 2016-01-28 | 2019-12-24 | Apple Inc. | Load speculation recovery |
US10437595B1 (en) | 2016-03-15 | 2019-10-08 | Apple Inc. | Load/store dependency predictor optimization for replayed loads |
US11106469B2 (en) | 2019-08-14 | 2021-08-31 | International Business Machines Corporation | Instruction selection mechanism with class-dependent age-array |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4180861A (en) * | 1978-03-31 | 1979-12-25 | Ncr Corporation | Selectively operable mask generator |
JPS55147744A (en) * | 1979-05-07 | 1980-11-17 | Hitachi Ltd | Memory controlling unit |
JPS6462764A (en) * | 1987-09-03 | 1989-03-09 | Agency Ind Science Techn | Vector computer |
WO1990010267A1 (en) * | 1989-02-24 | 1990-09-07 | Nexgen Microsystems | Distributed pipeline control for a computer |
US5095458A (en) * | 1990-04-02 | 1992-03-10 | Advanced Micro Devices, Inc. | Radix 4 carry lookahead tree and redundant cell therefor |
JPH0820949B2 (ja) * | 1991-11-26 | 1996-03-04 | 松下電器産業株式会社 | 情報処理装置 |
EP0583089B1 (de) * | 1992-08-12 | 2000-01-26 | Advanced Micro Devices, Inc. | Befehlsdecoder |
KR100248903B1 (ko) * | 1992-09-29 | 2000-03-15 | 야스카와 히데아키 | 수퍼스칼라마이크로프로세서에서의 적재 및 저장연산처리방법 및 시스템 |
US5450560A (en) * | 1992-12-21 | 1995-09-12 | Motorola, Inc. | Pointer for use with a buffer and method of operation |
US5467473A (en) * | 1993-01-08 | 1995-11-14 | International Business Machines Corporation | Out of order instruction load and store comparison |
JPH0793152A (ja) * | 1993-09-20 | 1995-04-07 | Fujitsu Ltd | マイクロプロセッサ制御装置 |
DE69427265T2 (de) * | 1993-10-29 | 2002-05-02 | Advanced Micro Devices Inc | Superskalarbefehlsdekoder |
US5724536A (en) * | 1994-01-04 | 1998-03-03 | Intel Corporation | Method and apparatus for blocking execution of and storing load operations during their execution |
US5689693A (en) * | 1994-04-26 | 1997-11-18 | Advanced Micro Devices, Inc. | Range finding circuit for selecting a consecutive sequence of reorder buffer entries using circular carry lookahead |
US5559975A (en) * | 1994-06-01 | 1996-09-24 | Advanced Micro Devices, Inc. | Program counter update mechanism |
US5745726A (en) * | 1995-03-03 | 1998-04-28 | Fujitsu, Ltd | Method and apparatus for selecting the oldest queued instructions without data dependencies |
US5745724A (en) * | 1996-01-26 | 1998-04-28 | Advanced Micro Devices, Inc. | Scan chain for rapidly identifying first or second objects of selected types in a sequential list |
US5754812A (en) * | 1995-10-06 | 1998-05-19 | Advanced Micro Devices, Inc. | Out-of-order load/store execution control |
US5748934A (en) * | 1996-05-31 | 1998-05-05 | Hewlett-Packard Company | Operand dependency tracking system and method for a processor that executes instructions out of order and that permits multiple precision data words |
-
1996
- 1996-10-23 US US08/740,119 patent/US5835747A/en not_active Expired - Lifetime
-
1997
- 1997-01-22 WO PCT/US1997/000294 patent/WO1997027538A1/en active IP Right Grant
- 1997-01-22 DE DE69736105T patent/DE69736105T2/de not_active Expired - Lifetime
- 1997-01-22 AU AU15309/97A patent/AU1530997A/en not_active Abandoned
- 1997-01-22 EP EP97901401A patent/EP0876646B1/de not_active Expired - Lifetime
- 1997-01-22 JP JP52687497A patent/JP3681761B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69736105T2 (de) | 2007-01-11 |
EP0876646A1 (de) | 1998-11-11 |
JP3681761B2 (ja) | 2005-08-10 |
WO1997027538A1 (en) | 1997-07-31 |
AU1530997A (en) | 1997-08-20 |
US5835747A (en) | 1998-11-10 |
EP0876646B1 (de) | 2006-06-14 |
JP2000515268A (ja) | 2000-11-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY |
|
8328 | Change in the person/name/address of the agent |
Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER, |