DE69731700D1 - Arithmetic circuit and arithmetic method - Google Patents

Arithmetic circuit and arithmetic method

Info

Publication number
DE69731700D1
DE69731700D1 DE69731700T DE69731700T DE69731700D1 DE 69731700 D1 DE69731700 D1 DE 69731700D1 DE 69731700 T DE69731700 T DE 69731700T DE 69731700 T DE69731700 T DE 69731700T DE 69731700 D1 DE69731700 D1 DE 69731700D1
Authority
DE
Germany
Prior art keywords
arithmetic
circuit
arithmetic circuit
arithmetic method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69731700T
Other languages
German (de)
Other versions
DE69731700T2 (en
Inventor
Gensuke Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69731700D1 publication Critical patent/DE69731700D1/en
Publication of DE69731700T2 publication Critical patent/DE69731700T2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Error Detection And Correction (AREA)
DE69731700T 1996-08-29 1997-02-05 Arithmetic Circuit and Arithmetic Method Expired - Fee Related DE69731700T2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP22861896 1996-08-29
JP22861896 1996-08-29
JP27614896A JP3678512B2 (en) 1996-08-29 1996-10-18 Multiplier circuit, adder circuit constituting the multiplier circuit, partial product bit compression method of the multiplier circuit, and large-scale semiconductor integrated circuit to which the multiplier circuit is applied
JP27614896 1996-10-18

Publications (2)

Publication Number Publication Date
DE69731700D1 true DE69731700D1 (en) 2004-12-30
DE69731700T2 DE69731700T2 (en) 2005-06-09

Family

ID=26528355

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69731700T Expired - Fee Related DE69731700T2 (en) 1996-08-29 1997-02-05 Arithmetic Circuit and Arithmetic Method

Country Status (5)

Country Link
US (3) US5920498A (en)
EP (3) EP1475697A1 (en)
JP (1) JP3678512B2 (en)
KR (2) KR100384567B1 (en)
DE (1) DE69731700T2 (en)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077308A (en) * 1999-06-28 2001-03-23 Ando Electric Co Ltd And circuit
US6611857B1 (en) * 2000-01-05 2003-08-26 Texas Instruments Incorporated Method and system for reducing power in a parallel-architecture multiplier
KR100423903B1 (en) * 2000-12-29 2004-03-24 삼성전자주식회사 High speed low power 4-2 compressor
US7315879B2 (en) * 2001-02-16 2008-01-01 Texas Instruments Incorporated Multiply-accumulate modules and parallel multipliers and methods of designing multiply-accumulate modules and parallel multipliers
US6877022B1 (en) * 2001-02-16 2005-04-05 Texas Instruments Incorporated Booth encoding circuit for a multiplier of a multiply-accumulate module
US20030158880A1 (en) * 2002-02-13 2003-08-21 Ng Kenneth Y. Booth encoder and partial products circuit
US6978426B2 (en) * 2002-04-10 2005-12-20 Broadcom Corporation Low-error fixed-width modified booth multiplier
KR100505491B1 (en) * 2002-10-02 2005-08-03 전자부품연구원 4:2 compressor for fast arithmetic unit
FI118654B (en) * 2002-11-06 2008-01-31 Nokia Corp Method and system for performing landing operations and apparatus
FI115862B (en) * 2002-11-06 2005-07-29 Nokia Corp Method and system for performing a multiplication operation and apparatus
US7159003B1 (en) * 2003-02-21 2007-01-02 S3 Graphics Co., Ltd. Method and apparatus for generating sign-digit format of sum of two numbers
US7308470B2 (en) * 2003-12-05 2007-12-11 Intel Corporation Smaller and lower power static mux circuitry in generating multiplier partial product signals
US7562106B2 (en) * 2004-08-07 2009-07-14 Ternarylogic Llc Multi-value digital calculating circuits, including multipliers
WO2006106581A1 (en) * 2005-03-31 2006-10-12 Fujitsu Limited Csa 5-3 compressing circuit and carrier-save adding circuit using the same
KR100681046B1 (en) * 2005-08-09 2007-02-08 현대자동차주식회사 Vehicle cover-step
JP5074425B2 (en) * 2006-02-15 2012-11-14 クゥアルコム・インコーポレイテッド Booth multiplier with extended reduced tree circuit configuration
US7720902B2 (en) * 2006-02-28 2010-05-18 Sony Corporation Entertainment Inc. Methods and apparatus for providing a reduction array
US20090063609A1 (en) * 2007-06-08 2009-03-05 Honkai Tam Static 4:2 Compressor with Fast Sum and Carryout
JP4988627B2 (en) * 2008-03-05 2012-08-01 ルネサスエレクトロニクス株式会社 Filter calculator and motion compensation device
JP5261738B2 (en) * 2009-01-15 2013-08-14 国立大学法人広島大学 Semiconductor device
CN102999312B (en) * 2012-12-20 2015-09-30 西安电子科技大学 The optimization method of base 16 booth multiplier
KR102072541B1 (en) 2018-07-31 2020-02-03 주식회사 아성기업 Vehicle subsidiary foot panel with automatic mode and manual mode exchange structure
CN109542393B (en) * 2018-11-19 2022-11-04 电子科技大学 Approximate 4-2 compressor and approximate multiplier
CN110515588B (en) * 2019-08-30 2024-02-02 上海寒武纪信息科技有限公司 Multiplier, data processing method, chip and electronic equipment
TWI707543B (en) * 2020-02-06 2020-10-11 崛智科技有限公司 Compressor, adder circuit and operation method thereof

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55105732A (en) * 1979-02-08 1980-08-13 Nippon Telegr & Teleph Corp <Ntt> Multiplier
JPS5731042A (en) * 1980-07-31 1982-02-19 Toshiba Corp Multiplaying and dividing circuits
JPS57121736A (en) * 1981-01-21 1982-07-29 Nippon Telegr & Teleph Corp <Ntt> Multiinput adder
JPS58211252A (en) * 1982-06-03 1983-12-08 Toshiba Corp Total adder
JPS593634A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Multiplier
JPS59139447A (en) * 1983-01-28 1984-08-10 Matsushita Electric Ind Co Ltd Full adder
JPS59211138A (en) * 1983-05-16 1984-11-29 Toshiba Corp Full adder circuit
US4575812A (en) * 1984-05-31 1986-03-11 Motorola, Inc. X×Y Bit array multiplier/accumulator circuit
JPS61262928A (en) * 1985-05-17 1986-11-20 Matsushita Electric Ind Co Ltd Cmos logical circuit
FR2611286B1 (en) * 1987-02-23 1989-04-21 Dassault Electronique MULTIPLIER INTEGRATED CIRCUIT, AND COMPOSITION METHOD THEREOF
US4901270A (en) * 1988-09-23 1990-02-13 Intel Corporation Four-to-two adder cell for parallel multiplication
JPH083787B2 (en) * 1988-10-21 1996-01-17 株式会社東芝 Unit adder and parallel multiplier
US5038315A (en) * 1989-05-15 1991-08-06 At&T Bell Laboratories Multiplier circuit
EP0447254A3 (en) * 1990-03-16 1993-07-28 C-Cube Microsystems Array multiplier
US5151875A (en) * 1990-03-16 1992-09-29 C-Cube Microsystems, Inc. MOS array multiplier cell
JPH081593B2 (en) * 1990-03-20 1996-01-10 富士通株式会社 Multiplier
US5040139A (en) * 1990-04-16 1991-08-13 Tran Dzung J Transmission gate multiplexer (TGM) logic circuits and multiplier architectures
JPH0492920A (en) * 1990-08-03 1992-03-25 Fujitsu Ltd One bit adder of five inputs/three outputs
JP2518551B2 (en) * 1990-10-31 1996-07-24 富士通株式会社 Multi-input adder circuit
JPH04287220A (en) * 1991-03-18 1992-10-12 Hitachi Ltd Multiplier circuit
US5268858A (en) * 1991-08-30 1993-12-07 Cyrix Corporation Method and apparatus for negating an operand
JPH0588852A (en) * 1991-09-27 1993-04-09 Sanyo Electric Co Ltd Partial product generating circuit and multiplying circuit
JPH05108308A (en) * 1991-10-14 1993-04-30 Fujitsu Ltd Multiplication circuit
JPH05150950A (en) * 1991-11-29 1993-06-18 Sony Corp Multiplier circuit
JPH06242928A (en) * 1993-02-22 1994-09-02 Nec Corp Adder and multiplying circuit using the same
FR2722590B1 (en) * 1994-07-15 1996-09-06 Sgs Thomson Microelectronics PARALLEL MULTIPLICATION LOGIC CIRCUIT
US5818747A (en) * 1995-01-27 1998-10-06 Sun Microsystems, Inc. Small, fast CMOS 4-2 carry-save adder cell
US5734601A (en) * 1995-01-30 1998-03-31 Cirrus Logic, Inc. Booth multiplier with low power, high performance input circuitry
TW421757B (en) * 1996-06-06 2001-02-11 Matsushita Electric Ind Co Ltd Arithmetic processor
JP3652447B2 (en) * 1996-07-24 2005-05-25 株式会社ルネサステクノロジ Tree circuit
JP3271932B2 (en) 1997-06-27 2002-04-08 ブラザー工業株式会社 Electrode array, image forming toner supply device, and image forming device
US5805491A (en) * 1997-07-11 1998-09-08 International Business Machines Corporation Fast 4-2 carry save adder using multiplexer logic

Also Published As

Publication number Publication date
EP1475697A1 (en) 2004-11-10
KR100449963B1 (en) 2004-09-24
JPH10124297A (en) 1998-05-15
EP0827069A3 (en) 1998-12-30
US5920498A (en) 1999-07-06
US6535902B2 (en) 2003-03-18
DE69731700T2 (en) 2005-06-09
US20010016865A1 (en) 2001-08-23
JP3678512B2 (en) 2005-08-03
EP0827069A2 (en) 1998-03-04
EP0827069B1 (en) 2004-11-24
KR19980032041A (en) 1998-07-25
KR100384567B1 (en) 2003-08-21
EP1475698A1 (en) 2004-11-10
US6240438B1 (en) 2001-05-29

Similar Documents

Publication Publication Date Title
DE69731700D1 (en) Arithmetic circuit and arithmetic method
DE69834401D1 (en) BUSINTERFACESYSTEM AND METHOD
DE69534700D1 (en) SEMICONDUCTOR ARRANGEMENTS AND METHOD
DE69522423T2 (en) Digitizer and method
DE69708879D1 (en) Z-AXIS INTERMEDIATE CONNECTION METHOD AND CIRCUIT
DE69621517T2 (en) Integrated monolithic microwave circuit and method
DE69534987D1 (en) CDMA demodulation circuit and demodulation method
DE69706043T2 (en) INTEGRATED CIRCUIT PROTECTION AND METHOD
DE69913180D1 (en) EXTRACTION UNITS AND METHOD
BR9704099A (en) Disassembly method of electronic device and disassembly device
DE69511080D1 (en) INTERFACE ARRANGEMENT AND METHOD
FI965091A0 (en) Calculation method and apparatus
DE69816818D1 (en) MAJORITY DECISION DEVICE AND CORRESPONDING METHOD
DE69707677D1 (en) DELAY CIRCUIT AND METHOD
DE69711825D1 (en) Lapping device and method
DE69736257D1 (en) Circuit and method for product sum calculation
DE69717216T2 (en) Circuit board tester and method therefor
DE19881476T1 (en) Drilling system and method
DE19782204T1 (en) Extension facility and procedure
DE69808362T2 (en) Multiplication method and multiplication circuit
DE69937428D1 (en) Common mode feedback circuit and method
DE69627948D1 (en) Arithmetic circuit with immediate recognition function and method for immediate recognition
DE69731809T2 (en) Character processing device and method
DE69532061D1 (en) Amplifier circuit and method
DE69530444D1 (en) Charger and method

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee