DE69718278D1 - Methode und System zur Einzel-Zyklus-Ausführung aufeinanderfolgender Iterationen einer Befehlsschleife - Google Patents

Methode und System zur Einzel-Zyklus-Ausführung aufeinanderfolgender Iterationen einer Befehlsschleife

Info

Publication number
DE69718278D1
DE69718278D1 DE69718278T DE69718278T DE69718278D1 DE 69718278 D1 DE69718278 D1 DE 69718278D1 DE 69718278 T DE69718278 T DE 69718278T DE 69718278 T DE69718278 T DE 69718278T DE 69718278 D1 DE69718278 D1 DE 69718278D1
Authority
DE
Germany
Prior art keywords
successive iterations
instruction loop
cycle execution
execution
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69718278T
Other languages
English (en)
Other versions
DE69718278T2 (de
Inventor
Timothy D Anderson
Jonathan H Shiell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69718278D1 publication Critical patent/DE69718278D1/de
Application granted granted Critical
Publication of DE69718278T2 publication Critical patent/DE69718278T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE69718278T 1996-10-31 1997-10-31 Methode und System zur Einzel-Zyklus-Ausführung aufeinanderfolgender Iterationen einer Befehlsschleife Expired - Lifetime DE69718278T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US2923096P 1996-10-31 1996-10-31

Publications (2)

Publication Number Publication Date
DE69718278D1 true DE69718278D1 (de) 2003-02-13
DE69718278T2 DE69718278T2 (de) 2003-08-21

Family

ID=21847948

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69718278T Expired - Lifetime DE69718278T2 (de) 1996-10-31 1997-10-31 Methode und System zur Einzel-Zyklus-Ausführung aufeinanderfolgender Iterationen einer Befehlsschleife

Country Status (4)

Country Link
US (1) US5951679A (de)
EP (1) EP0840208B1 (de)
JP (1) JPH10177482A (de)
DE (1) DE69718278T2 (de)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998036351A1 (fr) * 1997-02-17 1998-08-20 Hitachi, Ltd. Processeur de donnees
US6385720B1 (en) * 1997-07-14 2002-05-07 Matsushita Electric Industrial Co., Ltd. Branch prediction method and processor using origin information, relative position information and history information
EP0992916A1 (de) 1998-10-06 2000-04-12 Texas Instruments Inc. Digitaler Signalprozessor
EP1163577B1 (de) * 1999-03-17 2003-11-26 Infineon Technologies AG Cachen kurzer programmschleifen innerhalb eines instruktions-fifos
WO2001016702A1 (en) 1999-09-01 2001-03-08 Intel Corporation Register set used in multithreaded parallel processor architecture
EP1236097A4 (de) * 1999-09-01 2006-08-02 Intel Corp Verzweigungsbefehl zum prozessor
US6598155B1 (en) 2000-01-31 2003-07-22 Intel Corporation Method and apparatus for loop buffering digital signal processing instructions
US6963965B1 (en) 1999-11-30 2005-11-08 Texas Instruments Incorporated Instruction-programmable processor with instruction loop cache
EP1107110B1 (de) * 1999-11-30 2006-04-19 Texas Instruments Incorporated Befehlsschleifenspuffer
US6732203B2 (en) * 2000-01-31 2004-05-04 Intel Corporation Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus
US7649901B2 (en) 2000-02-08 2010-01-19 Mips Technologies, Inc. Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing
US20010052053A1 (en) * 2000-02-08 2001-12-13 Mario Nemirovsky Stream processing unit for a multi-streaming processor
US7032226B1 (en) * 2000-06-30 2006-04-18 Mips Technologies, Inc. Methods and apparatus for managing a buffer of events in the background
US7082552B2 (en) * 2000-02-08 2006-07-25 Mips Tech Inc Functional validation of a packet management unit
US7139901B2 (en) 2000-02-08 2006-11-21 Mips Technologies, Inc. Extended instruction set for packet processing applications
US7155516B2 (en) * 2000-02-08 2006-12-26 Mips Technologies, Inc. Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory
US7042887B2 (en) 2000-02-08 2006-05-09 Mips Technologies, Inc. Method and apparatus for non-speculative pre-fetch operation in data packet processing
US7502876B1 (en) 2000-06-23 2009-03-10 Mips Technologies, Inc. Background memory manager that determines if data structures fits in memory with memory state transactions map
US7065096B2 (en) * 2000-06-23 2006-06-20 Mips Technologies, Inc. Method for allocating memory space for limited packet head and/or tail growth
US7165257B2 (en) 2000-02-08 2007-01-16 Mips Technologies, Inc. Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts
US7058064B2 (en) 2000-02-08 2006-06-06 Mips Technologies, Inc. Queueing system for processors in packet routing operations
US6567895B2 (en) * 2000-05-31 2003-05-20 Texas Instruments Incorporated Loop cache memory and cache controller for pipelined microprocessors
US6829702B1 (en) * 2000-07-26 2004-12-07 International Business Machines Corporation Branch target cache and method for efficiently obtaining target path instructions for tight program loops
US7681018B2 (en) 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US20020184566A1 (en) 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
US6728856B2 (en) 2001-06-01 2004-04-27 Microchip Technology Incorporated Modified Harvard architecture processor having program memory space mapped to data memory space
US6604169B2 (en) 2001-06-01 2003-08-05 Microchip Technology Incorporated Modulo addressing based on absolute offset
US6601160B2 (en) 2001-06-01 2003-07-29 Microchip Technology Incorporated Dynamically reconfigurable data space
US6552625B2 (en) 2001-06-01 2003-04-22 Microchip Technology Inc. Processor with pulse width modulation generator with fault input prioritization
US20040021483A1 (en) * 2001-09-28 2004-02-05 Brian Boles Functional pathway configuration at a system/IC interface
US6552567B1 (en) 2001-09-28 2003-04-22 Microchip Technology Incorporated Functional pathway configuration at a system/IC interface
US7249248B2 (en) * 2002-11-25 2007-07-24 Intel Corporation Method, apparatus, and system for variable increment multi-index looping operations
JP4610218B2 (ja) * 2004-03-30 2011-01-12 ルネサスエレクトロニクス株式会社 情報処理装置
US7475231B2 (en) * 2005-11-14 2009-01-06 Texas Instruments Incorporated Loop detection and capture in the instruction queue
US20080229074A1 (en) * 2006-06-19 2008-09-18 International Business Machines Corporation Design Structure for Localized Control Caching Resulting in Power Efficient Control Logic
US20070294519A1 (en) * 2006-06-19 2007-12-20 Miller Laura F Localized Control Caching Resulting In Power Efficient Control Logic
US20090217017A1 (en) * 2008-02-26 2009-08-27 International Business Machines Corporation Method, system and computer program product for minimizing branch prediction latency
US9110683B2 (en) * 2008-08-15 2015-08-18 Apple Inc. Predicting branches for vector partitioning loops when processing vector instructions
US9753733B2 (en) 2012-06-15 2017-09-05 Apple Inc. Methods, apparatus, and processors for packing multiple iterations of loop in a loop buffer
US9557999B2 (en) 2012-06-15 2017-01-31 Apple Inc. Loop buffer learning
US9471322B2 (en) 2014-02-12 2016-10-18 Apple Inc. Early loop buffer mode entry upon number of mispredictions of exit condition exceeding threshold
US11294681B2 (en) * 2019-05-31 2022-04-05 Texas Instruments Incorporated Processing device with a microbranch target buffer for branch prediction using loop iteration count
US20230195517A1 (en) * 2021-12-22 2023-06-22 Advanced Micro Devices, Inc. Multi-Cycle Scheduler with Speculative Picking of Micro-Operations
US20240028339A1 (en) * 2022-07-25 2024-01-25 Apple Inc. Using a Next Fetch Predictor Circuit with Short Branches and Return Fetch Groups

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0743647B2 (ja) * 1982-03-18 1995-05-15 横河電機株式会社 データ処理装置における命令ループ捕捉機構
US4626988A (en) * 1983-03-07 1986-12-02 International Business Machines Corporation Instruction fetch look-aside buffer with loop mode control
JP2690921B2 (ja) * 1987-12-25 1997-12-17 株式会社日立製作所 情報処理装置
US4876642A (en) * 1988-01-19 1989-10-24 Gibson Glenn A Rules and apparatus for a loop capturing code buffer that prefetches instructions
DE68926701T2 (de) * 1988-08-09 1997-02-20 Matsushita Electric Ind Co Ltd Datenverarbeitungsgerät zur parallelen Dekodierung und parallelen Ausführung von Befehlen mit variabler Wortlänge
EP0449369B1 (de) * 1990-03-27 1998-07-29 Koninklijke Philips Electronics N.V. Datenverarbeitungssystem mit einem leistungsverbessernden Befehlscachespeicher
US5421020A (en) * 1993-01-08 1995-05-30 International Business Machines Corporation Counter register implementation for speculative execution of branch on count instructions
EP0651320B1 (de) * 1993-10-29 2001-05-23 Advanced Micro Devices, Inc. Superskalarbefehlsdekoder
US5943494A (en) * 1995-06-07 1999-08-24 International Business Machines Corporation Method and system for processing multiple branch instructions that write to count and link registers

Also Published As

Publication number Publication date
EP0840208A2 (de) 1998-05-06
EP0840208A3 (de) 1999-04-21
EP0840208B1 (de) 2003-01-08
US5951679A (en) 1999-09-14
DE69718278T2 (de) 2003-08-21
JPH10177482A (ja) 1998-06-30

Similar Documents

Publication Publication Date Title
DE69718278D1 (de) Methode und System zur Einzel-Zyklus-Ausführung aufeinanderfolgender Iterationen einer Befehlsschleife
DE69621694D1 (de) Verfahren und Anordnung zur transparenten Emulation einer Befehlssatzarchitektur
DE69613071D1 (de) Prozessor und Kontrollverfahren zur Ausführung richtiger Saturationsoperation
DE69738775D1 (de) Verfahren und einrichtung zur leistungssteuerung i
DE69737757D1 (de) System und Verfahren zur Speicher-Emulation
DE69519762D1 (de) Verfahren und System zur Ermöglichung einer effizienten Auswahl von Fernsehprogrammen
DE69824688D1 (de) System und Verfahren zur Leistungsoptimierung eines Rechnersystems
DE69534292D1 (de) Verfahren und System zur Dateifernübertragung
FI962887A0 (fi) Menetelmä ja järjestelmä kilpailujen automaattista ohjausta varten
DE69831358D1 (de) System und verfahren zur vereinfachung des weiterreichens
DE69904579D1 (de) System und verfahren zur schnellen ausführung von graphischen anwendungsprogrammen mit instruktionen aus schattierungssprachen
DE69914108D1 (de) System und verfahren zur steuerung von zufälligen zugriffen
DE69836795D1 (de) System und verfahren zur servosteuerung elektromagnetischer betätigungsvorrichtungen
DE69816682D1 (de) Verfahren und Vorrichtung zur Abgasbehandlung
DE60016427D1 (de) Verfahren und system zum herunterladen und zur steuerung der ausführung einer liste von kodeobjekten
DE69814155D1 (de) System und verfahren zur virtuellen eingabe
DE69816789D1 (de) Verfahren und system zur gestengesteuerten optionsauswahl
DE69229198D1 (de) Verzweigungsbefehlprozessor und Verfahren
DE69819264D1 (de) Verfahren und Einrichtung zur Granulierung
DE69720131D1 (de) System und Verfahren zur Perspektivetransformation
DE69517234D1 (de) System und Verfahren zur automatischen Frequenzregelung
DE69816509D1 (de) Verfahren zur Abgasbehandlung
DE60034759D1 (de) System und Verfahren zur Sendeleistungsregelung
DE69838154D1 (de) Belichtungseinheit, Belichtungssystem und Verfahren zur Herstellung einer Vorrichtung
DE69824823D1 (de) Methode zur abgasbehandlung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition