DE69704678D1 - Verfahren zum herstellen einer leiterplatteranordnung mit zinn/bleischicht - Google Patents
Verfahren zum herstellen einer leiterplatteranordnung mit zinn/bleischichtInfo
- Publication number
- DE69704678D1 DE69704678D1 DE69704678T DE69704678T DE69704678D1 DE 69704678 D1 DE69704678 D1 DE 69704678D1 DE 69704678 T DE69704678 T DE 69704678T DE 69704678 T DE69704678 T DE 69704678T DE 69704678 D1 DE69704678 D1 DE 69704678D1
- Authority
- DE
- Germany
- Prior art keywords
- tin
- producing
- pcb assembly
- lead layer
- layer pcb
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0302—Properties and characteristics in general
- H05K2201/0305—Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/0455—PTH for surface mount device [SMD], e.g. wherein solder flows through the PTH during mounting
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S428/00—Stock material or miscellaneous articles
- Y10S428/901—Printed circuit
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metallurgy (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB9626754.7A GB9626754D0 (en) | 1996-12-23 | 1996-12-23 | A pseudo duplex scheme |
PCT/GB1997/003532 WO1998028958A1 (en) | 1996-12-23 | 1997-12-22 | Method of making a printed circuit board having a tin/lead coating |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69704678D1 true DE69704678D1 (de) | 2001-05-31 |
DE69704678T2 DE69704678T2 (de) | 2001-08-02 |
Family
ID=10804943
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69704678T Expired - Fee Related DE69704678T2 (de) | 1996-12-23 | 1997-12-22 | Verfahren zum herstellen einer leiterplatteranordnung mit zinn/bleischicht |
Country Status (6)
Country | Link |
---|---|
US (1) | US6168854B1 (de) |
EP (1) | EP0947125B1 (de) |
AU (1) | AU5332098A (de) |
DE (1) | DE69704678T2 (de) |
GB (1) | GB9626754D0 (de) |
WO (1) | WO1998028958A1 (de) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6869870B2 (en) * | 1998-12-21 | 2005-03-22 | Megic Corporation | High performance system-on-chip discrete components using post passivation process |
US8421158B2 (en) * | 1998-12-21 | 2013-04-16 | Megica Corporation | Chip structure with a passive device and method for forming the same |
US6303423B1 (en) | 1998-12-21 | 2001-10-16 | Megic Corporation | Method for forming high performance system-on-chip using post passivation process |
US7531417B2 (en) * | 1998-12-21 | 2009-05-12 | Megica Corporation | High performance system-on-chip passive device using post passivation process |
US8178435B2 (en) | 1998-12-21 | 2012-05-15 | Megica Corporation | High performance system-on-chip inductor using post passivation process |
US6656370B1 (en) * | 2000-10-13 | 2003-12-02 | Lenora Toscano | Method for the manufacture of printed circuit boards |
US6509530B2 (en) * | 2001-06-22 | 2003-01-21 | Intel Corporation | Via intersect pad for electronic components and methods of manufacture |
US6759275B1 (en) | 2001-09-04 | 2004-07-06 | Megic Corporation | Method for making high-performance RF integrated circuits |
US6566611B2 (en) | 2001-09-26 | 2003-05-20 | Intel Corporation | Anti-tombstoning structures and methods of manufacture |
TWI236763B (en) * | 2003-05-27 | 2005-07-21 | Megic Corp | High performance system-on-chip inductor using post passivation process |
US7355282B2 (en) | 2004-09-09 | 2008-04-08 | Megica Corporation | Post passivation interconnection process and structures |
US8008775B2 (en) | 2004-09-09 | 2011-08-30 | Megica Corporation | Post passivation interconnection structures |
US7064279B2 (en) * | 2004-09-23 | 2006-06-20 | Motorola, Inc. | Circuit board having an overlapping via |
US8384189B2 (en) * | 2005-03-29 | 2013-02-26 | Megica Corporation | High performance system-on-chip using post passivation process |
CN1901163B (zh) * | 2005-07-22 | 2011-04-13 | 米辑电子股份有限公司 | 连续电镀制作线路组件的方法及线路组件结构 |
EP2503594A1 (de) | 2011-03-21 | 2012-09-26 | Dialog Semiconductor GmbH | Ball-/Padlayout einer integrierten Schaltungspackung mit optimiertem Signalrouting |
US10624208B1 (en) * | 2018-10-18 | 2020-04-14 | Arista Networks, Inc. | Landing pattern for ball grid array |
US11508683B2 (en) * | 2019-06-17 | 2022-11-22 | Western Digital Technologies, Inc. | Semiconductor device with die bumps aligned with substrate balls |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4515829A (en) * | 1983-10-14 | 1985-05-07 | Shipley Company Inc. | Through-hole plating |
DE3440668A1 (de) * | 1984-11-07 | 1986-05-07 | Dr.-Ing. Max Schlötter GmbH & Co KG, 7340 Geislingen | Verfahren zur erhaltung der loetbarkeit von bleizinn-ueberzuegen |
US4686015A (en) * | 1985-03-26 | 1987-08-11 | Allied Corporation | Nickel/indium alloy and method of using same in the manufacture of printed circuit boards |
US4804615A (en) * | 1985-08-08 | 1989-02-14 | Macdermid, Incorporated | Method for manufacture of printed circuit boards |
JP2675473B2 (ja) | 1992-01-13 | 1997-11-12 | 三洋電機株式会社 | フラットパッケージic半田ディップ型プリント配線板 |
DE4307784C2 (de) * | 1993-03-12 | 1996-02-22 | Korsten & Goossens Gue | Verfahren zum Herstellen von mit Pads versehenen Leiterplatten für die SMD-Bestückung |
-
1996
- 1996-12-23 GB GBGB9626754.7A patent/GB9626754D0/en active Pending
-
1997
- 1997-12-22 EP EP97950318A patent/EP0947125B1/de not_active Expired - Lifetime
- 1997-12-22 US US09/331,621 patent/US6168854B1/en not_active Expired - Fee Related
- 1997-12-22 AU AU53320/98A patent/AU5332098A/en not_active Abandoned
- 1997-12-22 WO PCT/GB1997/003532 patent/WO1998028958A1/en active IP Right Grant
- 1997-12-22 DE DE69704678T patent/DE69704678T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6168854B1 (en) | 2001-01-02 |
WO1998028958A1 (en) | 1998-07-02 |
DE69704678T2 (de) | 2001-08-02 |
EP0947125B1 (de) | 2001-04-25 |
EP0947125A1 (de) | 1999-10-06 |
AU5332098A (en) | 1998-07-17 |
GB9626754D0 (en) | 1997-02-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |