DE69700292D1 - Veränderbare digitale Verzögerungszelle - Google Patents

Veränderbare digitale Verzögerungszelle

Info

Publication number
DE69700292D1
DE69700292D1 DE69700292T DE69700292T DE69700292D1 DE 69700292 D1 DE69700292 D1 DE 69700292D1 DE 69700292 T DE69700292 T DE 69700292T DE 69700292 T DE69700292 T DE 69700292T DE 69700292 D1 DE69700292 D1 DE 69700292D1
Authority
DE
Germany
Prior art keywords
delay cell
digital delay
changeable digital
changeable
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69700292T
Other languages
English (en)
Other versions
DE69700292T2 (de
Inventor
Joachim Moll
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69700292D1 publication Critical patent/DE69700292D1/de
Application granted granted Critical
Publication of DE69700292T2 publication Critical patent/DE69700292T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/603—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors with coupled emitters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/62—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors
    • H03K17/6257—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors with several inputs only combined with selecting means
    • H03K17/6264—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors with several inputs only combined with selecting means using current steering means

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)
DE69700292T 1997-11-18 1997-11-18 Veränderbare digitale Verzögerungszelle Expired - Fee Related DE69700292T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP97120157A EP0853385B1 (de) 1997-11-18 1997-11-18 Veränderbare digitale Verzögerungszelle

Publications (2)

Publication Number Publication Date
DE69700292D1 true DE69700292D1 (de) 1999-07-29
DE69700292T2 DE69700292T2 (de) 1999-10-14

Family

ID=8227637

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69700292T Expired - Fee Related DE69700292T2 (de) 1997-11-18 1997-11-18 Veränderbare digitale Verzögerungszelle

Country Status (4)

Country Link
US (1) US6127871A (de)
EP (1) EP0853385B1 (de)
JP (1) JPH11317651A (de)
DE (1) DE69700292T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6618775B1 (en) * 1997-08-15 2003-09-09 Micron Technology, Inc. DSP bus monitoring apparatus and method
US6671652B2 (en) 2001-12-26 2003-12-30 Hewlett-Packard Devlopment Company, L.P. Clock skew measurement circuit on a microprocessor die
US6977538B2 (en) * 2002-10-18 2005-12-20 Agilent Technologies, Inc. Delay unit for periodic signals
JP4113447B2 (ja) * 2002-12-02 2008-07-09 テクトロニクス・インターナショナル・セールス・ゲーエムベーハー ジッタ付加回路及び方法並びにパルス列生成回路及び方法
US7085337B2 (en) * 2003-09-30 2006-08-01 Keyeye Communications Adaptive per-pair skew compensation method for extended reach differential transmission
US7332983B2 (en) * 2005-10-31 2008-02-19 Hewlett-Packard Development Company, L.P. Tunable delay line using selectively connected grounding means
US20140233582A1 (en) * 2012-08-29 2014-08-21 Marvell World Trade Ltd. Semaphore soft and hard hybrid architecture

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4795923A (en) * 1987-11-25 1989-01-03 Tektronix, Inc. Adjustable delay circuit
US4797586A (en) * 1987-11-25 1989-01-10 Tektronix, Inc. Controllable delay circuit
DE69126734T2 (de) * 1990-04-16 1997-10-23 Brooktree Corp Verzögerungsglied mit steuerbarer Verzögerung
FR2689339B1 (fr) * 1992-03-24 1996-12-13 Bull Sa Procede et dispositif de reglage de retard a plusieurs gammes.
US5434523A (en) * 1994-04-05 1995-07-18 Motorola, Inc. Circuit and method for adjusting a pulse width of a signal
JP3043241B2 (ja) * 1994-10-24 2000-05-22 沖電気工業株式会社 可変遅延回路

Also Published As

Publication number Publication date
JPH11317651A (ja) 1999-11-16
EP0853385B1 (de) 1999-06-23
EP0853385A1 (de) 1998-07-15
US6127871A (en) 2000-10-03
DE69700292T2 (de) 1999-10-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D.STAATES DELA

8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D. STAATES, US

8339 Ceased/non-payment of the annual fee