DE69636846D1 - Verfahren und Apparat zur Aufteilung von Lade- und Entladefunktionen in einer ATM-Schnittstelle - Google Patents

Verfahren und Apparat zur Aufteilung von Lade- und Entladefunktionen in einer ATM-Schnittstelle

Info

Publication number
DE69636846D1
DE69636846D1 DE69636846T DE69636846T DE69636846D1 DE 69636846 D1 DE69636846 D1 DE 69636846D1 DE 69636846 T DE69636846 T DE 69636846T DE 69636846 T DE69636846 T DE 69636846T DE 69636846 D1 DE69636846 D1 DE 69636846D1
Authority
DE
Germany
Prior art keywords
atm interface
unloading functions
splitting
loading
splitting loading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69636846T
Other languages
English (en)
Other versions
DE69636846T2 (de
Inventor
Rasoul M Oskouy
Denton E Gentry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of DE69636846D1 publication Critical patent/DE69636846D1/de
Application granted granted Critical
Publication of DE69636846T2 publication Critical patent/DE69636846T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5614—User Network Interface
    • H04L2012/5615—Network termination, e.g. NT1, NT2, PBX
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5614—User Network Interface
    • H04L2012/5616—Terminal equipment, e.g. codecs, synch.
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
DE69636846T 1995-07-07 1996-07-02 Verfahren und Apparat zur Aufteilung von Lade- und Entladefunktionen in einer ATM-Schnittstelle Expired - Fee Related DE69636846T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US499573 1983-05-31
US08/499,573 US5625625A (en) 1995-07-07 1995-07-07 Method and apparatus for partitioning data load and unload functions within an interface system for use with an asynchronous transfer mode system

Publications (2)

Publication Number Publication Date
DE69636846D1 true DE69636846D1 (de) 2007-03-08
DE69636846T2 DE69636846T2 (de) 2007-11-08

Family

ID=23985786

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69636846T Expired - Fee Related DE69636846T2 (de) 1995-07-07 1996-07-02 Verfahren und Apparat zur Aufteilung von Lade- und Entladefunktionen in einer ATM-Schnittstelle

Country Status (4)

Country Link
US (1) US5625625A (de)
EP (1) EP0752798B1 (de)
JP (1) JP3808548B2 (de)
DE (1) DE69636846T2 (de)

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US5878045A (en) * 1996-04-26 1999-03-02 Motorola, Inc. Method and apparatus for converting data streams in a cell based communications system
US6034945A (en) 1996-05-15 2000-03-07 Cisco Technology, Inc. Method and apparatus for per traffic flow buffer management
US5802051A (en) * 1996-06-10 1998-09-01 Telefonaktiebolaget Lm Ericsson Multiplexing of voice and data minicells
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US6487202B1 (en) 1997-06-30 2002-11-26 Cisco Technology, Inc. Method and apparatus for maximizing memory throughput
US6201813B1 (en) * 1997-06-30 2001-03-13 Cisco Technology, Inc. Method and apparatus for using ATM queues for segmentation and reassembly of data frames
US6026090A (en) * 1997-11-14 2000-02-15 Fore System, Inc. Method and system for receiving ATM cells from an ATM network by a host
US6526060B1 (en) 1997-12-05 2003-02-25 Cisco Technology, Inc. Dynamic rate-based, weighted fair scheduler with explicit rate feedback option
GB2332333B (en) * 1997-12-09 2003-01-15 Sony Uk Ltd An ATM re-assembly circuit and method
US6795442B1 (en) * 1998-04-23 2004-09-21 Emulex Design & Manufacturing Corporation System and method for scheduling message transmission and processing in a digital data network
US6570850B1 (en) 1998-04-23 2003-05-27 Giganet, Inc. System and method for regulating message flow in a digital data network
GB9821766D0 (en) 1998-10-06 1998-12-02 Sgs Thomson Microelectronics Data transfer
GB9821770D0 (en) 1998-10-06 1998-12-02 Sgs Thomson Microelectronics Data transfer
GB9821800D0 (en) 1998-10-06 1998-12-02 Sgs Thomson Microelectronics Data transfer
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GB9821763D0 (en) * 1998-10-06 1998-12-02 Sgs Thomson Microelectronics Data transfer
GB9821792D0 (en) 1998-10-06 1998-12-02 Sgs Thomson Microelectronics Data transfer
GB9821791D0 (en) 1998-10-06 1998-12-02 Sgs Thomson Microelectronics Data transfer
GB9821789D0 (en) 1998-10-06 1998-12-02 Sgs Thomson Microelectronics Jitter handling
US6269413B1 (en) 1998-10-30 2001-07-31 Hewlett Packard Company System with multiple dynamically-sized logical FIFOs sharing single memory and with read/write pointers independently selectable and simultaneously responsive to respective read/write FIFO selections
US6304936B1 (en) 1998-10-30 2001-10-16 Hewlett-Packard Company One-to-many bus bridge using independently and simultaneously selectable logical FIFOS
US6584121B1 (en) * 1998-11-13 2003-06-24 Lucent Technologies Switch architecture for digital multiplexed signals
US6810042B1 (en) * 1999-01-04 2004-10-26 Cisco Technology, Inc. Method of queuing traffic to many destinations covering a wide range of transmission speeds while minimizing buffer size
US6424658B1 (en) 1999-01-29 2002-07-23 Neomagic Corp. Store-and-forward network switch using an embedded DRAM
US6765911B1 (en) 1999-02-03 2004-07-20 International Business Machines Corporation Communications adapter for implementing communications in a network and providing multiple modes of communications
US6661774B1 (en) 1999-02-16 2003-12-09 Efficient Networks, Inc. System and method for traffic shaping packet-based signals
US6590897B1 (en) 1999-03-08 2003-07-08 Efficient Networks, Inc. System and method for bridging universal serial bus and asynchronous transfer mode communication links
US7020141B1 (en) * 1999-10-12 2006-03-28 Nortel Networks Limited ATM common part sub-layer device and method
US6775292B1 (en) 2000-01-24 2004-08-10 Cisco Technology, Inc. Method for servicing of multiple queues carrying voice over virtual circuits based on history
US6714562B1 (en) * 2000-03-10 2004-03-30 International Business Machines Corporation Method and apparatus for segmenting network traffic variable length frames
US6965603B1 (en) 2000-03-20 2005-11-15 Cortina Systems, Inc. Circuits for combining ATM and packet data on an optical fiber
US6810039B1 (en) 2000-03-30 2004-10-26 Azanda Network Devices, Inc. Processor-based architecture for facilitating integrated data transfer between both atm and packet traffic with a packet bus or packet link, including bidirectional atm-to-packet functionally for atm traffic
US6751224B1 (en) 2000-03-30 2004-06-15 Azanda Network Devices, Inc. Integrated ATM/packet segmentation-and-reassembly engine for handling both packet and ATM input data and for outputting both ATM and packet data
US6751214B1 (en) 2000-03-30 2004-06-15 Azanda Network Devices, Inc. Methods and apparatus for dynamically allocating bandwidth between ATM cells and packets
US7142558B1 (en) 2000-04-17 2006-11-28 Cisco Technology, Inc. Dynamic queuing control for variable throughput communication channels
US6934280B1 (en) 2000-05-04 2005-08-23 Nokia, Inc. Multiple services emulation over a single network service
US6694388B1 (en) * 2000-05-31 2004-02-17 3Com Corporation Dynamic queuing system incorporating multiple queues sharing a single memory
US7224693B1 (en) * 2000-08-11 2007-05-29 Ericsson Ab Long packet handling
US6925506B1 (en) * 2000-09-29 2005-08-02 Cypress Semiconductor Corp. Architecture for implementing virtual multiqueue fifos
US20020136220A1 (en) * 2000-10-02 2002-09-26 Shakuntala Anjanaiah Apparatus and method for an interface unit for data transfer between data processing units in the asynchronous transfer mode and in the I/O mode
KR100453349B1 (ko) * 2001-12-14 2004-10-15 엘지전자 주식회사 서로 다른 물리계층의 데이터 정합 장치 및 방법
US6804692B2 (en) * 2001-12-21 2004-10-12 Agere Systems, Inc. Method and apparatus for reassembly of data blocks within a network processor
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US7738496B1 (en) 2002-12-31 2010-06-15 Cypress Semiconductor Corporation Device that provides the functionality of dual-ported memory using single-ported memory for multiple clock domains
US7924845B2 (en) * 2003-09-30 2011-04-12 Mentor Graphics Corporation Message-based low latency circuit emulation signal transfer
US7934057B1 (en) 2003-12-24 2011-04-26 Cypress Semiconductor Corporation Logic for implementing a dual clock domain read access with predictable timing for bi-directional inputs/outputs
FR2877176B1 (fr) * 2004-10-22 2007-04-20 Agence Spatiale Europeenne Procede et dispositif pour ordonnancer et transmettre des paquets de donnees a partir d'un emetteur commun vers une pluralite d'utilisateurs partageant un canal de transmission coummun.
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US5548587A (en) * 1994-09-12 1996-08-20 Efficient Networks, Inc. Asynchronous transfer mode adapter for desktop applications

Also Published As

Publication number Publication date
JP3808548B2 (ja) 2006-08-16
EP0752798A2 (de) 1997-01-08
EP0752798A3 (de) 1999-05-19
US5625625A (en) 1997-04-29
DE69636846T2 (de) 2007-11-08
JPH09121209A (ja) 1997-05-06
EP0752798B1 (de) 2007-01-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee