DE69633474D1 - Adressierungsverfahren zur nicht-sequentiellen Ausführung von Ladebefehlen hinsichtlich Speicherungsbefehlen - Google Patents

Adressierungsverfahren zur nicht-sequentiellen Ausführung von Ladebefehlen hinsichtlich Speicherungsbefehlen

Info

Publication number
DE69633474D1
DE69633474D1 DE69633474T DE69633474T DE69633474D1 DE 69633474 D1 DE69633474 D1 DE 69633474D1 DE 69633474 T DE69633474 T DE 69633474T DE 69633474 T DE69633474 T DE 69633474T DE 69633474 D1 DE69633474 D1 DE 69633474D1
Authority
DE
Germany
Prior art keywords
instructions
respect
load
addressing method
sequential execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69633474T
Other languages
English (en)
Other versions
DE69633474T2 (de
Inventor
Michael A Simone
Michael C Shebanow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69633474D1 publication Critical patent/DE69633474D1/de
Publication of DE69633474T2 publication Critical patent/DE69633474T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Storage Device Security (AREA)
DE69633474T 1995-02-14 1996-02-08 Adressierungsverfahren zur nicht-sequentiellen Ausführung von Ladebefehlen hinsichtlich Speicherungsbefehlen Expired - Lifetime DE69633474T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38838995A 1995-02-14 1995-02-14
US388389 1995-02-14

Publications (2)

Publication Number Publication Date
DE69633474D1 true DE69633474D1 (de) 2004-11-04
DE69633474T2 DE69633474T2 (de) 2005-11-17

Family

ID=23533918

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69633474T Expired - Lifetime DE69633474T2 (de) 1995-02-14 1996-02-08 Adressierungsverfahren zur nicht-sequentiellen Ausführung von Ladebefehlen hinsichtlich Speicherungsbefehlen

Country Status (4)

Country Link
US (1) US5784586A (de)
EP (1) EP0727737B1 (de)
AT (1) ATE278214T1 (de)
DE (1) DE69633474T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6446224B1 (en) 1995-03-03 2002-09-03 Fujitsu Limited Method and apparatus for prioritizing and handling errors in a computer system
US5931957A (en) * 1997-03-31 1999-08-03 International Business Machines Corporation Support for out-of-order execution of loads and stores in a processor
US6021485A (en) * 1997-04-10 2000-02-01 International Business Machines Corporation Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching
US6070238A (en) * 1997-09-11 2000-05-30 International Business Machines Corporation Method and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instruction
US5987595A (en) * 1997-11-25 1999-11-16 Intel Corporation Method and apparatus for predicting when load instructions can be executed out-of order
US6141747A (en) * 1998-09-22 2000-10-31 Advanced Micro Devices, Inc. System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word
US6442677B1 (en) * 1999-06-10 2002-08-27 Advanced Micro Devices, Inc. Apparatus and method for superforwarding load operands in a microprocessor
US6523109B1 (en) 1999-10-25 2003-02-18 Advanced Micro Devices, Inc. Store queue multimatch detection
US6481251B1 (en) 1999-10-25 2002-11-19 Advanced Micro Devices, Inc. Store queue number assignment and tracking
US6857060B2 (en) 2001-03-30 2005-02-15 Intel Corporation System, apparatus and method for prioritizing instructions and eliminating useless instructions
US7318414B2 (en) * 2002-05-10 2008-01-15 Tmc Company Constant-speed multi-pressure fuel injection system for improved dynamic range in internal combustion engine
US7376817B2 (en) 2005-08-10 2008-05-20 P.A. Semi, Inc. Partial load/store forward prediction
US7904789B1 (en) * 2006-03-31 2011-03-08 Guillermo Rozas Techniques for detecting and correcting errors in a memory device
WO2008155833A1 (ja) * 2007-06-20 2008-12-24 Fujitsu Limited キャッシュメモリ制御装置およびキャッシュメモリ制御方法
GB2469299B (en) 2009-04-07 2011-02-16 Imagination Tech Ltd Ensuring consistency between a data cache and a main memory
US9128725B2 (en) 2012-05-04 2015-09-08 Apple Inc. Load-store dependency predictor content management
US9600289B2 (en) 2012-05-30 2017-03-21 Apple Inc. Load-store dependency predictor PC hashing
US9535695B2 (en) 2013-01-25 2017-01-03 Apple Inc. Completing load and store instructions in a weakly-ordered memory model
US9619230B2 (en) 2013-06-28 2017-04-11 International Business Machines Corporation Predictive fetching and decoding for selected instructions
US9513924B2 (en) * 2013-06-28 2016-12-06 Globalfoundries Inc. Predictor data structure for use in pipelined processing
US9710268B2 (en) 2014-04-29 2017-07-18 Apple Inc. Reducing latency for pointer chasing loads
US10514925B1 (en) 2016-01-28 2019-12-24 Apple Inc. Load speculation recovery
US10437595B1 (en) 2016-03-15 2019-10-08 Apple Inc. Load/store dependency predictor optimization for replayed loads

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59231652A (ja) * 1983-06-13 1984-12-26 Hitachi Ltd メモリアクセス・オ−バラツプ検出方式
WO1994008287A1 (en) * 1992-09-29 1994-04-14 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US5467473A (en) * 1993-01-08 1995-11-14 International Business Machines Corporation Out of order instruction load and store comparison
US5588126A (en) * 1993-12-30 1996-12-24 Intel Corporation Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system

Also Published As

Publication number Publication date
US5784586A (en) 1998-07-21
DE69633474T2 (de) 2005-11-17
EP0727737A3 (de) 1999-11-17
EP0727737A2 (de) 1996-08-21
EP0727737B1 (de) 2004-09-29
ATE278214T1 (de) 2004-10-15

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