DE69624195D1 - Markierter vorausladungsabstand-und befehlsdekoder von variabler länge, befehlssätze und ihre verwendungsweise - Google Patents

Markierter vorausladungsabstand-und befehlsdekoder von variabler länge, befehlssätze und ihre verwendungsweise

Info

Publication number
DE69624195D1
DE69624195D1 DE69624195T DE69624195T DE69624195D1 DE 69624195 D1 DE69624195 D1 DE 69624195D1 DE 69624195 T DE69624195 T DE 69624195T DE 69624195 T DE69624195 T DE 69624195T DE 69624195 D1 DE69624195 D1 DE 69624195D1
Authority
DE
Germany
Prior art keywords
command
variable length
sets
preload distance
marked variable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69624195T
Other languages
English (en)
Other versions
DE69624195T2 (de
Inventor
Christopher Phillips
Robert Divivier
Mario Nemirovsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Application granted granted Critical
Publication of DE69624195D1 publication Critical patent/DE69624195D1/de
Publication of DE69624195T2 publication Critical patent/DE69624195T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE69624195T 1995-05-26 1996-05-16 Markierter vorausladungsabstand-und befehlsdekoder von variabler länge, befehlssätze und ihre verwendungsweise Expired - Fee Related DE69624195T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/445,563 US6237074B1 (en) 1995-05-26 1995-05-26 Tagged prefetch and instruction decoder for variable length instruction set and method of operation
PCT/US1996/007101 WO1996037829A1 (en) 1995-05-26 1996-05-16 Tagged prefetch and instruction decoder for variable length instruction set and method of operation

Publications (2)

Publication Number Publication Date
DE69624195D1 true DE69624195D1 (de) 2002-11-14
DE69624195T2 DE69624195T2 (de) 2003-07-03

Family

ID=23769407

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69624195T Expired - Fee Related DE69624195T2 (de) 1995-05-26 1996-05-16 Markierter vorausladungsabstand-und befehlsdekoder von variabler länge, befehlssätze und ihre verwendungsweise

Country Status (5)

Country Link
US (1) US6237074B1 (de)
EP (1) EP0772821B1 (de)
KR (1) KR970705079A (de)
DE (1) DE69624195T2 (de)
WO (1) WO1996037829A1 (de)

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US8127121B2 (en) 1999-01-28 2012-02-28 Ati Technologies Ulc Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US7941647B2 (en) 1999-01-28 2011-05-10 Ati Technologies Ulc Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination
US8074055B1 (en) 1999-01-28 2011-12-06 Ati Technologies Ulc Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
US8121828B2 (en) 1999-01-28 2012-02-21 Ati Technologies Ulc Detecting conditions for transfer of execution from one computer instruction stream to another and executing transfer on satisfaction of the conditions
US6684322B1 (en) * 1999-08-30 2004-01-27 Intel Corporation Method and system for instruction length decode
US6934832B1 (en) * 2000-01-18 2005-08-23 Ati International Srl Exception mechanism for a computer
US6581138B2 (en) * 2000-02-29 2003-06-17 Stmicroelectronics, Inc. Branch-prediction driven instruction prefetch
US7149883B1 (en) * 2000-03-30 2006-12-12 Intel Corporation Method and apparatus selectively to advance a write pointer for a queue based on the indicated validity or invalidity of an instruction stored within the queue
US6931641B1 (en) * 2000-04-04 2005-08-16 International Business Machines Corporation Controller for multiple instruction thread processors
EP1150213B1 (de) * 2000-04-28 2012-01-25 TELEFONAKTIEBOLAGET LM ERICSSON (publ) Datenverarbeitungssystem und Verfahren
US6457115B1 (en) * 2000-06-15 2002-09-24 Advanced Micro Devices, Inc. Apparatus and method for generating 64 bit addresses using a 32 bit adder
US7366882B2 (en) * 2001-05-10 2008-04-29 Zohair Sahraoui Address calculation unit for an object oriented processor having differentiation circuitry for selectively operating micro-instructions
US6898694B2 (en) * 2001-06-28 2005-05-24 Intel Corporation High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle
US7305542B2 (en) * 2002-06-25 2007-12-04 Intel Corporation Instruction length decoder
DE10339458A1 (de) * 2002-08-28 2004-03-25 Denso Corp., Kariya Gasmessfühler und Verfahren zu dessen Herstellung
GB2393270B (en) * 2002-09-19 2005-07-27 Advanced Risc Mach Ltd Executing variable length instructions stored within a plurality of discrete memory address regions
US6895475B2 (en) * 2002-09-30 2005-05-17 Analog Devices, Inc. Prefetch buffer method and apparatus
US7370152B2 (en) * 2004-06-29 2008-05-06 Rambus Inc. Memory controller with prefetching capability
EP1868081A4 (de) * 2005-04-08 2008-08-13 Matsushita Electric Ind Co Ltd Prozessor
US7958436B2 (en) 2005-12-23 2011-06-07 Intel Corporation Performing a cyclic redundancy checksum operation responsive to a user-level instruction
US7925957B2 (en) * 2006-03-20 2011-04-12 Intel Corporation Validating data using processor instructions
US7908463B2 (en) * 2007-06-26 2011-03-15 Globalfoundries Inc. Immediate and displacement extraction and decode mechanism
US9164772B2 (en) * 2011-02-04 2015-10-20 Qualcomm Incorporated Hybrid queue for storing instructions from fetch queue directly in out-of-order queue or temporarily in in-order queue until space is available
US8898433B2 (en) * 2012-04-26 2014-11-25 Avago Technologies General Ip (Singapore) Pte. Ltd. Efficient extraction of execution sets from fetch sets
US8930678B2 (en) * 2012-04-26 2015-01-06 Intel Corporation Instruction and logic to length decode X86 instructions
US9983990B1 (en) * 2013-11-21 2018-05-29 Altera Corporation Configurable storage circuits with embedded processing and control circuitry
US11204768B2 (en) 2019-11-06 2021-12-21 Onnivation Llc Instruction length based parallel instruction demarcator
CN110995285B (zh) * 2019-12-27 2023-05-05 成都达安众科技有限公司 一种uhf rfid分步式指令解码方法及芯片

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US4620274A (en) * 1983-04-01 1986-10-28 Honeywell Information Systems Inc. Data available indicator for an exhausted operand string
US5142634A (en) * 1989-02-03 1992-08-25 Digital Equipment Corporation Branch prediction
US5768575A (en) * 1989-02-24 1998-06-16 Advanced Micro Devices, Inc. Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions
JP2505887B2 (ja) 1989-07-14 1996-06-12 富士通株式会社 命令処理システム
US5204953A (en) 1989-08-04 1993-04-20 Intel Corporation One clock address pipelining in segmentation unit
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US5259006A (en) 1990-04-18 1993-11-02 Quickturn Systems, Incorporated Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like
US5189319A (en) 1991-10-10 1993-02-23 Intel Corporation Power reducing buffer/latch circuit
WO1993018459A1 (en) * 1992-03-06 1993-09-16 Rambus Inc. Prefetching into a cache to minimize main memory access time and cache size in a computer system
US5254888A (en) 1992-03-27 1993-10-19 Picopower Technology Inc. Switchable clock circuit for microprocessors to thereby save power
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US5353420A (en) * 1992-08-10 1994-10-04 Intel Corporation Method and apparatus for decoding conditional jump instructions in a single clock in a computer processor
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US5887152A (en) * 1995-04-12 1999-03-23 Advanced Micro Devices, Inc. Load/store unit with multiple oldest outstanding instruction pointers for completing store and load/store miss instructions

Also Published As

Publication number Publication date
DE69624195T2 (de) 2003-07-03
KR970705079A (ko) 1997-09-06
WO1996037829A1 (en) 1996-11-28
EP0772821A1 (de) 1997-05-14
EP0772821B1 (de) 2002-10-09
US6237074B1 (en) 2001-05-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee