DE69623691D1 - Ein Gerät und Verfahren, das ein für Cache-Kollisionen weniger anfälliges Cache-Indizierungsverfahren vorsieht - Google Patents

Ein Gerät und Verfahren, das ein für Cache-Kollisionen weniger anfälliges Cache-Indizierungsverfahren vorsieht

Info

Publication number
DE69623691D1
DE69623691D1 DE69623691T DE69623691T DE69623691D1 DE 69623691 D1 DE69623691 D1 DE 69623691D1 DE 69623691 T DE69623691 T DE 69623691T DE 69623691 T DE69623691 T DE 69623691T DE 69623691 D1 DE69623691 D1 DE 69623691D1
Authority
DE
Germany
Prior art keywords
cache
provides
less prone
collisions
indexing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69623691T
Other languages
English (en)
Other versions
DE69623691T2 (de
Inventor
Bodo K Parady
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of DE69623691D1 publication Critical patent/DE69623691D1/de
Application granted granted Critical
Publication of DE69623691T2 publication Critical patent/DE69623691T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69623691T 1995-06-02 1996-05-28 Ein Gerät und Verfahren, das ein für Cache-Kollisionen weniger anfälliges Cache-Indizierungsverfahren vorsieht Expired - Fee Related DE69623691T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/459,755 US5649143A (en) 1995-06-02 1995-06-02 Apparatus and method for providing a cache indexing scheme less susceptible to cache collisions

Publications (2)

Publication Number Publication Date
DE69623691D1 true DE69623691D1 (de) 2002-10-24
DE69623691T2 DE69623691T2 (de) 2003-05-22

Family

ID=23826025

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69623691T Expired - Fee Related DE69623691T2 (de) 1995-06-02 1996-05-28 Ein Gerät und Verfahren, das ein für Cache-Kollisionen weniger anfälliges Cache-Indizierungsverfahren vorsieht

Country Status (4)

Country Link
US (1) US5649143A (de)
EP (2) EP0745940B1 (de)
JP (1) JPH09223069A (de)
DE (1) DE69623691T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5860151A (en) * 1995-12-07 1999-01-12 Wisconsin Alumni Research Foundation Data cache fast address calculation system and method
US6000014A (en) * 1997-04-14 1999-12-07 International Business Machines Corporation Software-managed programmable congruence class caching mechanism
US6233647B1 (en) * 1998-07-07 2001-05-15 Silicon Graphics, Inc. Hashed direct-mapped texture cache
DE10101552A1 (de) * 2001-01-15 2002-07-25 Infineon Technologies Ag Cache-Speicher und Verfahren zur Adressierung
US7299318B2 (en) * 2001-12-20 2007-11-20 Sun Microsystems, Inc. Method for reducing cache conflict misses
US7177853B1 (en) * 2002-02-21 2007-02-13 Emc Corporation Cache management via statistically adjusted time stamp queue
US7058642B2 (en) * 2002-03-20 2006-06-06 Intel Corporation Method and data structure for a low memory overhead database
DE10258767A1 (de) * 2002-12-16 2004-07-15 Infineon Technologies Ag Verfahren zum Betrieb eines Cache-Speichers
US7051184B2 (en) * 2003-05-06 2006-05-23 Sun Microsystems, Inc. Method and apparatus for mapping memory addresses to corresponding cache entries
US7606994B1 (en) * 2004-11-10 2009-10-20 Sun Microsystems, Inc. Cache memory system including a partially hashed index
US8327057B1 (en) 2007-04-16 2012-12-04 Juniper Networks, Inc. Ordering write bursts to memory
WO2008155846A1 (ja) * 2007-06-20 2008-12-24 Fujitsu Limited メモリ装置および情報処理装置
CN103279430B (zh) * 2012-07-27 2015-11-04 中南大学 图形处理单元中的缓存索引映射方法及装置
ES2546072T3 (es) * 2012-09-14 2015-09-18 Barcelona Supercomputing Center-Centro Nacional De Supercomputación Dispositivo para controlar el acceso a una estructura de memoria caché
US10296457B2 (en) * 2017-03-30 2019-05-21 Intel Corporation Reducing conflicts in direct mapped caches

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5379393A (en) * 1992-05-14 1995-01-03 The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantations Cache memory system for vector processing
WO1994003856A1 (en) * 1992-08-07 1994-02-17 Massachusetts Institute Of Technology Column-associative cache
US5509135A (en) * 1992-09-25 1996-04-16 Digital Equipment Corporation Multi-index multi-way set-associative cache

Also Published As

Publication number Publication date
DE69623691T2 (de) 2003-05-22
EP1227405A2 (de) 2002-07-31
JPH09223069A (ja) 1997-08-26
EP0745940B1 (de) 2002-09-18
EP1227405A3 (de) 2003-05-07
EP0745940A1 (de) 1996-12-04
US5649143A (en) 1997-07-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee