DE69623146D1 - Verfahren und Vorrichtung zum Koordinieren der Benutzung von physikalischen Registern in einem Mikroprozessor - Google Patents

Verfahren und Vorrichtung zum Koordinieren der Benutzung von physikalischen Registern in einem Mikroprozessor

Info

Publication number
DE69623146D1
DE69623146D1 DE69623146T DE69623146T DE69623146D1 DE 69623146 D1 DE69623146 D1 DE 69623146D1 DE 69623146 T DE69623146 T DE 69623146T DE 69623146 T DE69623146 T DE 69623146T DE 69623146 D1 DE69623146 D1 DE 69623146D1
Authority
DE
Germany
Prior art keywords
instruction
register
physical
microprocessor
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69623146T
Other languages
English (en)
Other versions
DE69623146T2 (de
Inventor
Deforest W Tovey
Michael C Shebanow
John Gmuender
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69623146D1 publication Critical patent/DE69623146D1/de
Publication of DE69623146T2 publication Critical patent/DE69623146T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Advance Control (AREA)
  • Retry When Errors Occur (AREA)
  • Hardware Redundancy (AREA)
DE69623146T 1995-02-14 1996-02-08 Verfahren und Vorrichtung zum Koordinieren der Benutzung von physikalischen Registern in einem Mikroprozessor Expired - Lifetime DE69623146T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US38836495A 1995-02-14 1995-02-14

Publications (2)

Publication Number Publication Date
DE69623146D1 true DE69623146D1 (de) 2002-10-02
DE69623146T2 DE69623146T2 (de) 2003-07-24

Family

ID=23533813

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69623146T Expired - Lifetime DE69623146T2 (de) 1995-02-14 1996-02-08 Verfahren und Vorrichtung zum Koordinieren der Benutzung von physikalischen Registern in einem Mikroprozessor

Country Status (4)

Country Link
US (1) US5740414A (de)
EP (1) EP0727735B1 (de)
AT (1) ATE223081T1 (de)
DE (1) DE69623146T2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6446224B1 (en) 1995-03-03 2002-09-03 Fujitsu Limited Method and apparatus for prioritizing and handling errors in a computer system
JPH1097423A (ja) * 1996-09-20 1998-04-14 Hitachi Ltd ループ処理の並列実行制御に適したレジスタ構成を有するプロセッサ
US5881305A (en) * 1996-12-13 1999-03-09 Advanced Micro Devices, Inc. Register rename stack for a microprocessor
EP0863460B1 (de) * 1997-03-03 2005-08-24 International Business Machines Corporation Verwaltung von umbenannten Register in einem superskalaren Rechnersystem
US5974525A (en) * 1997-12-05 1999-10-26 Intel Corporation System for allowing multiple instructions to use the same logical registers by remapping them to separate physical segment registers when the first is being utilized
US6253338B1 (en) 1998-12-21 2001-06-26 International Business Machines Corporation System for tracing hardware counters utilizing programmed performance monitor to generate trace interrupt after each branch instruction or at the end of each code basic block
US6338134B1 (en) 1998-12-29 2002-01-08 International Business Machines Corporation Method and system in a superscalar data processing system for the efficient processing of an instruction by moving only pointers to data
US6591359B1 (en) * 1998-12-31 2003-07-08 Intel Corporation Speculative renaming of data-processor registers
US6336191B1 (en) 1999-03-08 2002-01-01 International Business Machines Corporation Method and system for clock compensation in instruction level tracing in a symmetrical multi-processing system
US6421758B1 (en) 1999-07-26 2002-07-16 International Business Machines Corporation Method and system for super-fast updating and reading of content addressable memory with a bypass circuit
US20050120191A1 (en) * 2003-12-02 2005-06-02 Intel Corporation (A Delaware Corporation) Checkpoint-based register reclamation
US7529913B2 (en) * 2003-12-23 2009-05-05 Intel Corporation Late allocation of registers
US7487337B2 (en) * 2004-09-30 2009-02-03 Intel Corporation Back-end renaming in a continual flow processor pipeline
US7478276B2 (en) * 2005-02-10 2009-01-13 International Business Machines Corporation Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor
US7409589B2 (en) * 2005-05-27 2008-08-05 International Business Machines Corporation Method and apparatus for reducing number of cycles required to checkpoint instructions in a multi-threaded processor
US7904789B1 (en) * 2006-03-31 2011-03-08 Guillermo Rozas Techniques for detecting and correcting errors in a memory device
US20130173885A1 (en) * 2011-12-30 2013-07-04 Advanced Micro Devices, Inc. Processor and Methods of Adjusting a Branch Misprediction Recovery Mode
US9471325B2 (en) * 2013-07-12 2016-10-18 Qualcomm Incorporated Method and apparatus for selective renaming in a microprocessor
US10884746B2 (en) * 2017-08-18 2021-01-05 International Business Machines Corporation Determining and predicting affiliated registers based on dynamic runtime control flow analysis
US10884747B2 (en) 2017-08-18 2021-01-05 International Business Machines Corporation Prediction of an affiliated register
US11150908B2 (en) 2017-08-18 2021-10-19 International Business Machines Corporation Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence
US10908911B2 (en) 2017-08-18 2021-02-02 International Business Machines Corporation Predicting and storing a predicted target address in a plurality of selected locations
US10884745B2 (en) 2017-08-18 2021-01-05 International Business Machines Corporation Providing a predicted target address to multiple locations based on detecting an affiliated relationship
US11150904B2 (en) 2017-08-18 2021-10-19 International Business Machines Corporation Concurrent prediction of branch addresses and update of register contents
US10534609B2 (en) 2017-08-18 2020-01-14 International Business Machines Corporation Code-specific affiliated register prediction
US10719328B2 (en) 2017-08-18 2020-07-21 International Business Machines Corporation Determining and predicting derived values used in register-indirect branching
US11200062B2 (en) * 2019-08-26 2021-12-14 Apple Inc. History file for previous register mapping storage and last reference indication

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0297265B1 (de) * 1987-07-01 1994-12-14 International Business Machines Corporation Befehlssteuerungsvorrichtung für ein Computersystem
US4901233A (en) * 1987-07-20 1990-02-13 International Business Machines Corporation Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries
US5197132A (en) * 1990-06-29 1993-03-23 Digital Equipment Corporation Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery
EP0514763A3 (en) * 1991-05-20 1993-08-25 Motorola, Inc. A data processor having a logical register content-addressable memory
US5355457A (en) * 1991-05-21 1994-10-11 Motorola, Inc. Data processor for performing simultaneous instruction retirement and backtracking
US5694564A (en) * 1993-01-04 1997-12-02 Motorola, Inc. Data processing system a method for performing register renaming having back-up capability

Also Published As

Publication number Publication date
EP0727735A2 (de) 1996-08-21
EP0727735B1 (de) 2002-08-28
EP0727735A3 (de) 1997-07-02
DE69623146T2 (de) 2003-07-24
ATE223081T1 (de) 2002-09-15
US5740414A (en) 1998-04-14

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8332 No legal effect for de
8370 Indication related to discontinuation of the patent is to be deleted
8364 No opposition during term of opposition