DE69620591D1 - Erweiterte Adressierung für mehrere Geräte von einem einzelnen parallelen Ein-/Ausgabetor - Google Patents

Erweiterte Adressierung für mehrere Geräte von einem einzelnen parallelen Ein-/Ausgabetor

Info

Publication number
DE69620591D1
DE69620591D1 DE69620591T DE69620591T DE69620591D1 DE 69620591 D1 DE69620591 D1 DE 69620591D1 DE 69620591 T DE69620591 T DE 69620591T DE 69620591 T DE69620591 T DE 69620591T DE 69620591 D1 DE69620591 D1 DE 69620591D1
Authority
DE
Germany
Prior art keywords
output port
multiple devices
parallel input
single parallel
extended addressing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69620591T
Other languages
English (en)
Other versions
DE69620591T2 (de
Inventor
Darrell L Cox
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69620591D1 publication Critical patent/DE69620591D1/de
Application granted granted Critical
Publication of DE69620591T2 publication Critical patent/DE69620591T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G06F12/0661—Configuration or reconfiguration with centralised address assignment and decentralised selection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
DE69620591T 1996-05-20 1996-10-21 Erweiterte Adressierung für mehrere Geräte von einem einzelnen parallelen Ein-/Ausgabetor Expired - Fee Related DE69620591T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/650,724 US5901325A (en) 1996-05-20 1996-05-20 Extended addressing to multiple devices on a single parallel I/O port

Publications (2)

Publication Number Publication Date
DE69620591D1 true DE69620591D1 (de) 2002-05-16
DE69620591T2 DE69620591T2 (de) 2002-09-26

Family

ID=24610026

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69620591T Expired - Fee Related DE69620591T2 (de) 1996-05-20 1996-10-21 Erweiterte Adressierung für mehrere Geräte von einem einzelnen parallelen Ein-/Ausgabetor

Country Status (4)

Country Link
US (1) US5901325A (de)
EP (1) EP0809187B1 (de)
JP (1) JPH1049476A (de)
DE (1) DE69620591T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6073183A (en) * 1995-03-31 2000-06-06 Intel Corporation Transparent communication with multiple devices over a single serial or parallel port of a computer
JPH11168524A (ja) * 1997-12-05 1999-06-22 Canon Inc 通信制御装置および通信制御装置のデータ処理方法およびコンピュータが読み出し可能なプログラムを格納した記憶媒体
NZ508654A (en) * 1998-05-23 2003-03-28 Aristocrat Technologies Au Secured inter-processor and virtual device communications system
US6240472B1 (en) * 1998-10-22 2001-05-29 Microsoft Corporation Method and system for sharing a communications port
US6282586B1 (en) * 1998-10-28 2001-08-28 3Com Corporation Method in an operating system, a method and system for supporting multiple hardware devices from a single communications port
US6697884B1 (en) * 2000-01-03 2004-02-24 Genesis Microchip, Inc. Communication protocol for serial peripheral devices
US6268745B1 (en) 2000-04-20 2001-07-31 Hewlett-Packard Co. Wired-and bus interface circuit for galvanically isolating nodes
US6609172B1 (en) 2000-04-20 2003-08-19 Hewlett-Packard Development Company, L.P. Breaking up a bus to determine the connection topology and dynamic addressing
US6789182B1 (en) * 2000-11-13 2004-09-07 Kevin Jay Brothers System and method for logging computer event data and physical components of a complex distributed system
CH694899A5 (fr) * 2000-11-29 2005-08-31 Volotek Sa Systeme d'acquisition de donnees et jeu de cartes electroniques pour un tel systeme.
US20020144024A1 (en) * 2001-03-30 2002-10-03 Kumpf David A. Method and system for assigning peripheral devices to logical ports of a network peripheral server
US6973509B2 (en) * 2001-05-14 2005-12-06 International Business Machines Corporation Automatic frame identification, door status, and frame count detection system
US6799235B2 (en) * 2002-01-02 2004-09-28 Intel Corporation Daisy chain latency reduction
US7661026B2 (en) * 2003-05-27 2010-02-09 International Business Machines Corporation Access by distributed computers to a same hardware resource
JP3960278B2 (ja) * 2003-08-13 2007-08-15 ヤマハ株式会社 接続設定プログラム
EP2220849B1 (de) * 2007-12-12 2019-03-13 Nokia Technologies Oy Adressenzuweisungsprotokoll
KR20110132055A (ko) * 2010-06-01 2011-12-07 삼성전자주식회사 Ｉｄ 설정 시스템, ｉｄ 설정 방법 및 이를 이용한 디스플레이 장치

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4794520A (en) * 1987-03-30 1988-12-27 C-Guard Laboratories, Inc. Interface system for computer port sharing of multiple devices
US5276443A (en) * 1991-03-27 1994-01-04 Xircom, Inc. Parallel port multiplexor for PC parallel port
US5457785A (en) * 1993-02-10 1995-10-10 Elonex Technologies, Inc. CPU-independent and device-driver transparent system for translating a computer's internal bus signals onto an intermediate bus and further translating onto an expansion bus
US5555436A (en) * 1993-12-10 1996-09-10 Intel Corporation Apparatus for allowing multiple parallel port devices to share a single parallel port
US5619722A (en) * 1994-01-18 1997-04-08 Teramar Group, Inc. Addressable communication port expander
US5557741A (en) * 1994-04-28 1996-09-17 Dell Usa, L.P. Test apparatus and method for a computer parallel port
US5555374A (en) * 1994-08-26 1996-09-10 Systech Computer Corporation System and method for coupling a plurality of peripheral devices to a host computer through a host computer parallel port
US5623610A (en) * 1994-10-31 1997-04-22 Intel Corporation System for assigning geographical addresses in a hierarchical serial bus by enabling upstream port and selectively enabling disabled ports at power on/reset

Also Published As

Publication number Publication date
EP0809187B1 (de) 2002-04-10
EP0809187A1 (de) 1997-11-26
JPH1049476A (ja) 1998-02-20
US5901325A (en) 1999-05-04
DE69620591T2 (de) 2002-09-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

8339 Ceased/non-payment of the annual fee