DE69616883D1 - Anordnung von Puffern und Übertragungsleitungen zum Speisen von Logikgattern mit Taktsignalen - Google Patents

Anordnung von Puffern und Übertragungsleitungen zum Speisen von Logikgattern mit Taktsignalen

Info

Publication number
DE69616883D1
DE69616883D1 DE69616883T DE69616883T DE69616883D1 DE 69616883 D1 DE69616883 D1 DE 69616883D1 DE 69616883 T DE69616883 T DE 69616883T DE 69616883 T DE69616883 T DE 69616883T DE 69616883 D1 DE69616883 D1 DE 69616883D1
Authority
DE
Germany
Prior art keywords
buffers
arrangement
clock signals
transmission lines
logic gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69616883T
Other languages
English (en)
Other versions
DE69616883T2 (de
Inventor
Philip W Diodato
Harry Thomas Weston
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
AT&T IPM Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp, AT&T IPM Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69616883D1 publication Critical patent/DE69616883D1/de
Publication of DE69616883T2 publication Critical patent/DE69616883T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/15046—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a tapped delay line

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69616883T 1995-06-30 1996-06-18 Anordnung von Puffern und Übertragungsleitungen zum Speisen von Logikgattern mit Taktsignalen Expired - Fee Related DE69616883T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/497,350 US5519350A (en) 1995-06-30 1995-06-30 Circuitry for delivering a signal to different load elements located in an electronic system

Publications (2)

Publication Number Publication Date
DE69616883D1 true DE69616883D1 (de) 2001-12-20
DE69616883T2 DE69616883T2 (de) 2002-07-04

Family

ID=23976509

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69616883T Expired - Fee Related DE69616883T2 (de) 1995-06-30 1996-06-18 Anordnung von Puffern und Übertragungsleitungen zum Speisen von Logikgattern mit Taktsignalen

Country Status (6)

Country Link
US (1) US5519350A (de)
EP (1) EP0751620B1 (de)
JP (1) JPH0923149A (de)
KR (1) KR970004352A (de)
DE (1) DE69616883T2 (de)
TW (1) TW315450B (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5777529A (en) * 1996-10-10 1998-07-07 Northern Telecom Limited Integrated circuit assembly for distributed broadcasting of high speed chip input signals
FR2773020B1 (fr) * 1997-12-24 2000-03-10 Sgs Thomson Microelectronics Circuit de distribution d'horloge dans un circuit integre
US6606587B1 (en) * 1999-04-14 2003-08-12 Hewlett-Packard Development Company, L.P. Method and apparatus for estimating elmore delays within circuit designs
US6501706B1 (en) * 2000-08-22 2002-12-31 Burnell G. West Time-to-digital converter
US20060044016A1 (en) 2004-08-24 2006-03-02 Gasper Martin J Jr Integrated circuit with signal skew adjusting cell selected from cell library
FR3024619B1 (fr) * 2014-08-01 2016-07-29 Pyxalis Circuit integre photorepete avec compensation des retards de propagation de signaux, notamment de signaux d'horloge

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3586871A (en) * 1969-05-23 1971-06-22 Bell Telephone Labor Inc Phase responsive switching system
US3751591A (en) * 1972-06-20 1973-08-07 Ibm Zero skew clock distribution system
US4247817A (en) * 1978-05-15 1981-01-27 Teradyne, Inc. Transmitting electrical signals with a transmission time independent of distance between transmitter and receiver
US5387885A (en) * 1990-05-03 1995-02-07 University Of North Carolina Salphasic distribution of timing signals for the synchronization of physically separated entities
JP3112784B2 (ja) * 1993-09-24 2000-11-27 日本電気株式会社 クロック信号分配回路

Also Published As

Publication number Publication date
KR970004352A (ko) 1997-01-29
DE69616883T2 (de) 2002-07-04
US5519350A (en) 1996-05-21
JPH0923149A (ja) 1997-01-21
TW315450B (de) 1997-09-11
EP0751620B1 (de) 2001-11-14
EP0751620A1 (de) 1997-01-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee