DE69532307D1 - Ausdrucks-Propagierung für hierarchische Netzlisten - Google Patents

Ausdrucks-Propagierung für hierarchische Netzlisten

Info

Publication number
DE69532307D1
DE69532307D1 DE69532307T DE69532307T DE69532307D1 DE 69532307 D1 DE69532307 D1 DE 69532307D1 DE 69532307 T DE69532307 T DE 69532307T DE 69532307 T DE69532307 T DE 69532307T DE 69532307 D1 DE69532307 D1 DE 69532307D1
Authority
DE
Germany
Prior art keywords
net lists
hierarchical net
expression propagation
propagation
expression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69532307T
Other languages
English (en)
Other versions
DE69532307T2 (de
Inventor
Celimo P Hernandez
Robyn D Coultas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Application granted granted Critical
Publication of DE69532307D1 publication Critical patent/DE69532307D1/de
Publication of DE69532307T2 publication Critical patent/DE69532307T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE69532307T 1994-04-06 1995-04-05 Ausdrucks-Propagierung für hierarchisches Netzlisten Expired - Fee Related DE69532307T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/223,924 US5548524A (en) 1994-04-06 1994-04-06 Expression promotion for hierarchical netlisting
US223924 1994-04-06

Publications (2)

Publication Number Publication Date
DE69532307D1 true DE69532307D1 (de) 2004-01-29
DE69532307T2 DE69532307T2 (de) 2004-10-14

Family

ID=22838549

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69532307T Expired - Fee Related DE69532307T2 (de) 1994-04-06 1995-04-05 Ausdrucks-Propagierung für hierarchisches Netzlisten

Country Status (3)

Country Link
US (1) US5548524A (de)
EP (1) EP0676707B1 (de)
DE (1) DE69532307T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2816495A (en) * 1994-06-03 1996-01-04 Synopsys, Inc. Method and apparatus for estimating the power dissipated by a digital circuit
US5815402A (en) * 1996-06-07 1998-09-29 Micron Technology, Inc. System and method for changing the connected behavior of a circuit design schematic
US5808896A (en) * 1996-06-10 1998-09-15 Micron Technology, Inc. Method and system for creating a netlist allowing current measurement through a sub-circuit
US5875115A (en) * 1996-08-06 1999-02-23 Micron Technology, Inc. System and method for scoping global nets in a flat netlist
US5901064A (en) * 1996-08-06 1999-05-04 Micron Technology, Inc. System and method for scoping global nets in a hierarchical netlist
US5896300A (en) * 1996-08-30 1999-04-20 Avant| Corporation Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits by filtering timing error bounds for layout critical nets
US6516456B1 (en) * 1997-01-27 2003-02-04 Unisys Corporation Method and apparatus for selectively viewing nets within a database editor tool
US6009249A (en) * 1997-06-13 1999-12-28 Micron Technology, Inc. Automated load determination for partitioned simulation
US6134513A (en) * 1997-10-23 2000-10-17 Intel Corporation Method and apparatus for simulating large, hierarchical microelectronic resistor circuits
US6009252A (en) * 1998-03-05 1999-12-28 Avant! Corporation Methods, apparatus and computer program products for determining equivalencies between integrated circuit schematics and layouts using color symmetrizing matrices
US6243849B1 (en) * 1998-03-13 2001-06-05 Lsi Logic Corporation Method and apparatus for netlist filtering and cell placement
US6272671B1 (en) 1998-09-11 2001-08-07 Lsi Logic Corporation Extractor and schematic viewer for a design representation, and associated method
US6577992B1 (en) 1999-05-07 2003-06-10 Nassda Corporation Transistor level circuit simulator using hierarchical data
US6738953B1 (en) * 2001-06-01 2004-05-18 Virage Logic Corp. System and method for memory characterization
DE10160513B4 (de) * 2001-10-31 2012-02-23 Qimonda Ag Verfahren zur Verarbeitung von Daten, die Parameter bezüglich einer Anzahl Bauelemente einer elektrischen Schaltung darstellen
US20030093504A1 (en) * 2001-10-31 2003-05-15 Tilmann Neunhoeffer Method for processing data containing information about an electronic circuit having a plurality of hierarchically organized networks, computer readable storage medium and data processing system containing computer-executable instructions for performing the method
US6842750B2 (en) * 2002-03-27 2005-01-11 Lsi Logic Corporation Symbolic simulation driven netlist simplification
US6842888B2 (en) 2002-04-23 2005-01-11 Freescale Semiconductor, Inc. Method and apparatus for hierarchically restructuring portions of a hierarchical database based on selected attributes
KR100459731B1 (ko) * 2002-12-04 2004-12-03 삼성전자주식회사 반도체 집적회로의 시뮬레이션을 위한 인터커넥션 영향을포함한 선택적 연결정보를 생성하는 장치 및 그 방법
US7287236B2 (en) 2004-09-30 2007-10-23 Alcatel Lucent Electronic device connectivity analysis methods and systems
US7367006B1 (en) * 2005-01-11 2008-04-29 Cadence Design Systems, Inc. Hierarchical, rules-based, general property visualization and editing method and system
GB0619537D0 (en) * 2006-10-04 2006-11-15 Mephisto Design Automation Nv Method and apparatus for the simultaneous multi-level and/or multi-simulator design optimization of electronic circuits

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4831543A (en) * 1986-02-21 1989-05-16 Harris Semiconductor (Patents) Inc. Hierarchical net list derivation system
US5212650A (en) * 1986-09-12 1993-05-18 Digital Equipment Corporation Procedure and data structure for synthesis and transformation of logic circuit designs
US5150308A (en) * 1986-09-12 1992-09-22 Digital Equipment Corporation Parameter and rule creation and modification mechanism for use by a procedure for synthesis of logic circuit designs
US5029102A (en) * 1987-06-08 1991-07-02 International Business Machines, Corp. Logical synthesis
US5301318A (en) * 1988-05-13 1994-04-05 Silicon Systems, Inc. Hierarchical netlist extraction tool
US5247468A (en) * 1988-09-27 1993-09-21 Tektronix, Inc. System for calculating and displaying user-defined output parameters describing behavior of subcircuits of a simulated circuit
US4967367A (en) * 1988-11-21 1990-10-30 Vlsi Technology, Inc. Synthetic netlist system and method
US5210699A (en) * 1989-12-18 1993-05-11 Siemens Components, Inc. Process for extracting logic from transistor and resistor data representations of circuits
US5384710A (en) * 1990-03-13 1995-01-24 National Semiconductor Corporation Circuit level netlist generation
US5278769A (en) * 1991-04-12 1994-01-11 Lsi Logic Corporation Automatic logic model generation from schematic data base
US5262959A (en) * 1990-12-07 1993-11-16 Hewlett-Packard Co. Representation and processing of hierarchical block designs
EP0490478A2 (de) * 1990-12-14 1992-06-17 Tektronix Inc. Automatische Kompilierung von Modellgleichungen in einem gradientbasierten Analogsimulator

Also Published As

Publication number Publication date
EP0676707B1 (de) 2003-12-17
DE69532307T2 (de) 2004-10-14
EP0676707A2 (de) 1995-10-11
EP0676707A3 (de) 1996-07-10
US5548524A (en) 1996-08-20

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Legal Events

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8339 Ceased/non-payment of the annual fee