DE69524846T2 - Arbitervorrichtung - Google Patents

Arbitervorrichtung

Info

Publication number
DE69524846T2
DE69524846T2 DE69524846T DE69524846T DE69524846T2 DE 69524846 T2 DE69524846 T2 DE 69524846T2 DE 69524846 T DE69524846 T DE 69524846T DE 69524846 T DE69524846 T DE 69524846T DE 69524846 T2 DE69524846 T2 DE 69524846T2
Authority
DE
Germany
Prior art keywords
arbitervorrichtung
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69524846T
Other languages
English (en)
Other versions
DE69524846D1 (de
Inventor
Osman O Oktay
Edward A Summit
Gregory F Beck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of DE69524846D1 publication Critical patent/DE69524846D1/de
Application granted granted Critical
Publication of DE69524846T2 publication Critical patent/DE69524846T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
DE69524846T 1994-11-04 1995-10-30 Arbitervorrichtung Expired - Lifetime DE69524846T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/336,056 US5557783A (en) 1994-11-04 1994-11-04 Arbitration device for arbitrating access requests from first and second processors having different first and second clocks

Publications (2)

Publication Number Publication Date
DE69524846D1 DE69524846D1 (de) 2002-02-07
DE69524846T2 true DE69524846T2 (de) 2002-07-11

Family

ID=23314378

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69524846T Expired - Lifetime DE69524846T2 (de) 1994-11-04 1995-10-30 Arbitervorrichtung

Country Status (4)

Country Link
US (1) US5557783A (de)
EP (1) EP0710911B1 (de)
JP (1) JP3689463B2 (de)
DE (1) DE69524846T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5805871A (en) * 1995-07-21 1998-09-08 Ricoh Company Ltd. System and method for phase-synchronous, flexible-frequency clocking and messaging
US5805882A (en) * 1996-07-19 1998-09-08 Compaq Computer Corporation Computer system and method for replacing obsolete or corrupt boot code contained within reprogrammable memory with new boot code supplied from an external source through a data port
JP3524337B2 (ja) 1997-07-25 2004-05-10 キヤノン株式会社 バス管理装置及びそれを有する複合機器の制御装置
US6035360A (en) * 1997-10-29 2000-03-07 International Business Machines Corporation Multi-port SRAM access control using time division multiplexed arbitration
US6401176B1 (en) * 1997-11-14 2002-06-04 Agere Systems Guardian Corp. Multiple agent use of a multi-ported shared memory
US6314499B1 (en) * 1997-11-14 2001-11-06 Lucent Technologies Inc. Non-preemptive memory locking mechanism in a shared resource system
GB9802096D0 (en) * 1998-01-30 1998-03-25 Sgs Thomson Microelectronics Shared memory access
US6205522B1 (en) * 1998-04-15 2001-03-20 Diamond Multimedia Systems, Inc. DSP code swapping with continuous DSP execution
US6456628B1 (en) * 1998-04-17 2002-09-24 Intelect Communications, Inc. DSP intercommunication network
US6363492B1 (en) 1998-04-30 2002-03-26 Compaq Computer Corporation Computer method and apparatus to force boot block recovery
US6240519B1 (en) 1998-04-30 2001-05-29 Compaq Computer Corporation Computer method and apparatus to prompt for administrative password to flash a corrupted non-volatile memory
US6188249B1 (en) * 1998-06-30 2001-02-13 Sun Microsystems, Inc. Asymmetric arbiter with fast signal path
JP2001034530A (ja) * 1999-07-16 2001-02-09 Mitsubishi Electric Corp マイクロコンピュータおよびメモリアクセス制御方法
US6640275B1 (en) * 1999-12-22 2003-10-28 Nortel Networks Limited System and method for data transfer between buses having different speeds
US6629253B1 (en) * 1999-12-30 2003-09-30 Intel Corporation System for efficient management of memory access requests from a planar video overlay data stream using a time delay
US6920572B2 (en) * 2000-11-15 2005-07-19 Texas Instruments Incorporated Unanimous voting for disabling of shared component clocking in a multicore DSP device
JP2004171411A (ja) * 2002-11-21 2004-06-17 Hitachi Global Storage Technologies Netherlands Bv データ記憶装置及びバッファメモリの管理方法
TWI350451B (en) * 2007-09-06 2011-10-11 Ite Tech Inc Integrated memory control apparatus
KR102285749B1 (ko) * 2014-11-10 2021-08-05 삼성전자주식회사 세마포어 기능을 갖는 시스템 온 칩 및 그것의 세마포어 구현 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4764865A (en) * 1982-06-21 1988-08-16 International Business Machines Corp. Circuit for allocating memory cycles to two processors that share memory
JPS63316153A (ja) * 1987-06-18 1988-12-23 Nec Corp 同期式バス制御装置
US5005151A (en) * 1988-05-13 1991-04-02 Dallas Semiconductor Corporation Interleaved arbitration scheme for interfacing parallel and serial ports to a parallel system port
US5179667A (en) * 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
US5193193A (en) * 1988-09-14 1993-03-09 Silicon Graphics, Inc. Bus control system for arbitrating requests with predetermined on/off time limitations
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5144692A (en) * 1989-05-17 1992-09-01 International Business Machines Corporation System for controlling access by first system to portion of main memory dedicated exclusively to second system to facilitate input/output processing via first system
US5696899A (en) 1992-11-18 1997-12-09 Canon Kabushiki Kaisha Method and apparatus for adaptively determining the format of data packets carried on a local area network
US5611046A (en) 1992-11-18 1997-03-11 Canon Kabushiki Kaisha Method and apparatus for interfacing a peripheral to a local area network
JPH06161870A (ja) * 1992-11-26 1994-06-10 Nec Corp デュアルポートｒａｍ回路

Also Published As

Publication number Publication date
JP3689463B2 (ja) 2005-08-31
US5557783A (en) 1996-09-17
DE69524846D1 (de) 2002-02-07
EP0710911A1 (de) 1996-05-08
JPH08227401A (ja) 1996-09-03
EP0710911B1 (de) 2002-01-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition