DE69521089D1 - Vektordatenumgehungsmechanismus für einen Vektorrechner - Google Patents

Vektordatenumgehungsmechanismus für einen Vektorrechner

Info

Publication number
DE69521089D1
DE69521089D1 DE69521089T DE69521089T DE69521089D1 DE 69521089 D1 DE69521089 D1 DE 69521089D1 DE 69521089 T DE69521089 T DE 69521089T DE 69521089 T DE69521089 T DE 69521089T DE 69521089 D1 DE69521089 D1 DE 69521089D1
Authority
DE
Germany
Prior art keywords
vector
bypass mechanism
data bypass
calculator
vector data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69521089T
Other languages
English (en)
Other versions
DE69521089T2 (de
Inventor
Toshihiko Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69521089D1 publication Critical patent/DE69521089D1/de
Application granted granted Critical
Publication of DE69521089T2 publication Critical patent/DE69521089T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8076—Details on data register access
    • G06F15/8084—Special arrangements thereof, e.g. mask or switch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
DE69521089T 1994-09-02 1995-09-01 Vektordatenumgehungsmechanismus für einen Vektorrechner Expired - Fee Related DE69521089T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6209961A JPH0877143A (ja) 1994-09-02 1994-09-02 ベクトルデータ処理装置

Publications (2)

Publication Number Publication Date
DE69521089D1 true DE69521089D1 (de) 2001-07-05
DE69521089T2 DE69521089T2 (de) 2001-11-15

Family

ID=16581544

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69521089T Expired - Fee Related DE69521089T2 (de) 1994-09-02 1995-09-01 Vektordatenumgehungsmechanismus für einen Vektorrechner

Country Status (5)

Country Link
US (1) US5802384A (de)
EP (1) EP0700005B1 (de)
JP (1) JPH0877143A (de)
CA (1) CA2157435C (de)
DE (1) DE69521089T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100274988A1 (en) * 2002-02-04 2010-10-28 Mimar Tibet Flexible vector modes of operation for SIMD processor
US7793084B1 (en) 2002-07-22 2010-09-07 Mimar Tibet Efficient handling of vector high-level language conditional constructs in a SIMD processor
US7873812B1 (en) 2004-04-05 2011-01-18 Tibet MIMAR Method and system for efficient matrix multiplication in a SIMD processor architecture
JP2009104494A (ja) * 2007-10-25 2009-05-14 Nec Computertechno Ltd ベクトル処理装置
US9424042B2 (en) * 2011-12-06 2016-08-23 Intel Corporation System, apparatus and method for translating vector instructions

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6057467A (ja) * 1983-09-09 1985-04-03 Nec Corp ベクトルデ−タ処理装置
EP0167959B1 (de) * 1984-07-02 1992-05-06 Nec Corporation Rechner-Vektorregisterverarbeitung
US4837730A (en) * 1987-02-06 1989-06-06 Scientific Computer Systems Corporation Linking scalar results directly to scalar operation inputs on a bidirectional databus in a computer which superpositions vector and scalar operations
US4888679A (en) * 1988-01-11 1989-12-19 Digital Equipment Corporation Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements
JPH0769821B2 (ja) * 1988-03-04 1995-07-31 日本電気株式会社 情報処理装置におけるバイパスライン制御方式
US5151995A (en) * 1988-08-05 1992-09-29 Cray Research, Inc. Method and apparatus for producing successive calculated results in a high-speed computer functional unit using low-speed VLSI components
JPH0253142A (ja) * 1988-08-17 1990-02-22 Hitachi Ltd ベクトルレジスタ診断方式
JPH02288975A (ja) * 1989-02-17 1990-11-28 Nec Eng Ltd ベクトル演算装置
US5555384A (en) * 1989-12-01 1996-09-10 Silicon Graphics, Inc. Rescheduling conflicting issued instructions by delaying one conflicting instruction into the same pipeline stage as a third non-conflicting instruction
JP2988965B2 (ja) * 1990-06-07 1999-12-13 株式会社東芝 パイプライン情報処理回路
US5590365A (en) * 1990-03-30 1996-12-31 Kabushiki Kaisha Toshiba Pipeline information processing circuit for floating point operations

Also Published As

Publication number Publication date
CA2157435C (en) 2000-05-16
EP0700005B1 (de) 2001-05-30
JPH0877143A (ja) 1996-03-22
DE69521089T2 (de) 2001-11-15
US5802384A (en) 1998-09-01
EP0700005A1 (de) 1996-03-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee