DE69500949D1 - Vereinfachtes Kontaktierungsverfahren für CMOS von hoher Dichte - Google Patents

Vereinfachtes Kontaktierungsverfahren für CMOS von hoher Dichte

Info

Publication number
DE69500949D1
DE69500949D1 DE69500949T DE69500949T DE69500949D1 DE 69500949 D1 DE69500949 D1 DE 69500949D1 DE 69500949 T DE69500949 T DE 69500949T DE 69500949 T DE69500949 T DE 69500949T DE 69500949 D1 DE69500949 D1 DE 69500949D1
Authority
DE
Germany
Prior art keywords
high density
contacting process
density cmos
simplified contacting
simplified
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69500949T
Other languages
English (en)
Other versions
DE69500949T2 (de
Inventor
Reid Stuart Bennett
Yee Dennis Sek-On
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69500949D1 publication Critical patent/DE69500949D1/de
Application granted granted Critical
Publication of DE69500949T2 publication Critical patent/DE69500949T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/141—Self-alignment coat gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Drying Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69500949T 1994-06-30 1995-05-19 Vereinfachtes Kontaktierungsverfahren für CMOS von hoher Dichte Expired - Fee Related DE69500949T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/269,856 US5420057A (en) 1994-06-30 1994-06-30 Simplified contact method for high density CMOS

Publications (2)

Publication Number Publication Date
DE69500949D1 true DE69500949D1 (de) 1997-12-04
DE69500949T2 DE69500949T2 (de) 1998-05-28

Family

ID=23028935

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69500949T Expired - Fee Related DE69500949T2 (de) 1994-06-30 1995-05-19 Vereinfachtes Kontaktierungsverfahren für CMOS von hoher Dichte

Country Status (4)

Country Link
US (1) US5420057A (de)
EP (1) EP0690491B1 (de)
JP (1) JP3124907B2 (de)
DE (1) DE69500949T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5506161A (en) * 1994-10-24 1996-04-09 Motorola, Inc. Method of manufacturing graded channels underneath the gate electrode extensions
US5960318A (en) * 1995-10-27 1999-09-28 Siemens Aktiengesellschaft Borderless contact etch process with sidewall spacer and selective isotropic etch process
US5783475A (en) * 1995-11-13 1998-07-21 Motorola, Inc. Method of forming a spacer
KR100206878B1 (ko) * 1995-12-29 1999-07-01 구본준 반도체소자 제조방법
TW201007885A (en) * 2008-07-18 2010-02-16 Nec Electronics Corp Manufacturing method of semiconductor device, and semiconductor device
US8575683B1 (en) * 2012-05-16 2013-11-05 United Microelectronics Corp. Semiconductor device and method of fabricating the same
US9269792B2 (en) 2014-06-09 2016-02-23 International Business Machines Corporation Method and structure for robust finFET replacement metal gate integration

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4169270A (en) * 1976-12-09 1979-09-25 Fairchild Camera And Instrument Corporation Insulated-gate field-effect transistor with self-aligned contact hole to source or drain
US5153145A (en) * 1989-10-17 1992-10-06 At&T Bell Laboratories Fet with gate spacer
FR2663157B1 (fr) * 1990-06-12 1992-08-07 Thomson Csf Procede d'autoalignement des contacts metalliques sur un dispositif semiconducteur et semiconducteur autoaligne.
US5234850A (en) * 1990-09-04 1993-08-10 Industrial Technology Research Institute Method of fabricating a nitride capped MOSFET for integrated circuits
JPH04179238A (ja) * 1990-11-14 1992-06-25 Nec Corp Ｍｉｓトランジスタの製造方法
US5171700A (en) * 1991-04-01 1992-12-15 Sgs-Thomson Microelectronics, Inc. Field effect transistor structure and method
US5244823A (en) * 1991-05-21 1993-09-14 Sharp Kabushiki Kaisha Process for fabricating a semiconductor device
US5330925A (en) * 1992-06-18 1994-07-19 At&T Bell Laboratories Method for making a MOS device
US5229326A (en) * 1992-06-23 1993-07-20 Micron Technology, Inc. Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device
US5338698A (en) * 1992-12-18 1994-08-16 International Business Machines Corporation Method of fabricating an ultra-short channel field effect transistor
US5364804A (en) * 1993-11-03 1994-11-15 Taiwan Semiconductor Manufacturing Company Nitride cap sidewall oxide protection from BOE etch

Also Published As

Publication number Publication date
JP3124907B2 (ja) 2001-01-15
DE69500949T2 (de) 1998-05-28
EP0690491B1 (de) 1997-10-29
EP0690491A1 (de) 1996-01-03
JPH0846197A (ja) 1996-02-16
US5420057A (en) 1995-05-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee