DE69424944T2 - Datenreduktion in einem system zur analysierung von geometrischen datenbanken - Google Patents

Datenreduktion in einem system zur analysierung von geometrischen datenbanken

Info

Publication number
DE69424944T2
DE69424944T2 DE69424944T DE69424944T DE69424944T2 DE 69424944 T2 DE69424944 T2 DE 69424944T2 DE 69424944 T DE69424944 T DE 69424944T DE 69424944 T DE69424944 T DE 69424944T DE 69424944 T2 DE69424944 T2 DE 69424944T2
Authority
DE
Germany
Prior art keywords
group
shape
model
models
design rule
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69424944T
Other languages
German (de)
English (en)
Other versions
DE69424944D1 (de
Inventor
Allen Baisuck
L. Fairbank
K. Gowen
R. Henriksen
W. Hoover
A. Huckabay
Eric Rogoyski
G. Salecker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Application granted granted Critical
Publication of DE69424944D1 publication Critical patent/DE69424944D1/de
Publication of DE69424944T2 publication Critical patent/DE69424944T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE69424944T 1993-09-20 1994-09-20 Datenreduktion in einem system zur analysierung von geometrischen datenbanken Expired - Lifetime DE69424944T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/124,330 US5440720A (en) 1993-09-20 1993-09-20 Architecture and method for data reduction in a system for analyzing geometric databases
PCT/US1994/010626 WO1995008811A1 (en) 1993-09-20 1994-09-20 Data reduction in a system for analyzing geometric databases

Publications (2)

Publication Number Publication Date
DE69424944D1 DE69424944D1 (de) 2000-07-20
DE69424944T2 true DE69424944T2 (de) 2000-10-19

Family

ID=22414239

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69424944T Expired - Lifetime DE69424944T2 (de) 1993-09-20 1994-09-20 Datenreduktion in einem system zur analysierung von geometrischen datenbanken

Country Status (4)

Country Link
US (1) US5440720A (Direct)
EP (1) EP0721624B1 (Direct)
DE (1) DE69424944T2 (Direct)
WO (1) WO1995008811A1 (Direct)

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US7715642B1 (en) * 1995-06-06 2010-05-11 Hewlett-Packard Development Company, L.P. Bitmap image compressing
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US5812415A (en) * 1996-04-05 1998-09-22 Cadence Design Systems, Inc. Method and apparatus for enhancing performance of design verification systems
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US5980092A (en) * 1996-11-19 1999-11-09 Unisys Corporation Method and apparatus for optimizing a gated clock structure using a standard optimization tool
US5956256A (en) * 1996-11-19 1999-09-21 Unisys Corporation Method and apparatus for optimizing a circuit design having multi-paths therein
US5864487A (en) * 1996-11-19 1999-01-26 Unisys Corporation Method and apparatus for identifying gated clocks within a circuit design using a standard optimization tool
US5960184A (en) * 1996-11-19 1999-09-28 Unisys Corporation Method and apparatus for providing optimization parameters to a logic optimizer tool
US5802075A (en) * 1997-01-16 1998-09-01 Unisys Corporation Distributed test pattern generation
US5912820A (en) * 1997-01-22 1999-06-15 Unisys Corporation Method and apparatus for distributing a clock tree within a hierarchical circuit design
US6516456B1 (en) 1997-01-27 2003-02-04 Unisys Corporation Method and apparatus for selectively viewing nets within a database editor tool
US6718520B1 (en) 1997-01-27 2004-04-06 Unisys Corporation Method and apparatus for selectively providing hierarchy to a circuit design
US7076410B1 (en) 1997-01-27 2006-07-11 Unisys Corporation Method and apparatus for efficiently viewing a number of selected components using a database editor tool
US6684376B1 (en) 1997-01-27 2004-01-27 Unisys Corporation Method and apparatus for selecting components within a circuit design database
US6708144B1 (en) 1997-01-27 2004-03-16 Unisys Corporation Spreadsheet driven I/O buffer synthesis process
US6910200B1 (en) 1997-01-27 2005-06-21 Unisys Corporation Method and apparatus for associating selected circuit instances and for performing a group operation thereon
US6754879B1 (en) 1997-01-27 2004-06-22 Unisys Corporation Method and apparatus for providing modularity to a behavioral description of a circuit design
US6701289B1 (en) 1997-01-27 2004-03-02 Unisys Corporation Method and apparatus for using a placement tool to manipulate cell substitution lists
US6009250A (en) * 1997-09-30 1999-12-28 Synopsys, Inc. Selective flattening in layout areas in computer implemented integrated circuit design
JPH11233581A (ja) * 1998-02-13 1999-08-27 Mitsubishi Electric Corp ウェーハテスト方法
US7340698B1 (en) 1998-07-22 2008-03-04 Magma Design Automation, Inc. Method of estimating performance of integrated circuit designs by finding scalars for strongly coupled components
US6499129B1 (en) * 1998-07-22 2002-12-24 Circuit Semantics, Inc. Method of estimating performance of integrated circuit designs
US6470477B1 (en) 1999-12-23 2002-10-22 Koninklijke Philips Electronics N.V. Methods for converting features to a uniform micron technology in an integrated circuit design and apparatus for doing the same
US6539519B1 (en) * 2000-05-31 2003-03-25 Mark D. Meeker Spatial characteristic and logical hierarchy based manner for compactly storing IC design data and related operations
US6889370B1 (en) 2000-06-20 2005-05-03 Unisys Corporation Method and apparatus for selecting and aligning cells using a placement tool
US6546532B1 (en) 2000-06-20 2003-04-08 Unisys Corporation Method and apparatus for traversing and placing cells using a placement tool
DE10149021B4 (de) * 2001-09-28 2006-04-27 Infineon Technologies Ag Datenverarbeitungssystem zum Entwurf eines Layouts einer integrierten elektronischen Schaltung aus einer Vielzahl von elektronischen Bauelementen
US20030217026A1 (en) * 2002-01-31 2003-11-20 Steven Teig Structure for storing a plurality os sub-networks
US6954910B2 (en) * 2002-01-31 2005-10-11 Cadence Design Systems, Inc. Method and apparatus for producing a circuit description of a design
DE10206658B4 (de) * 2002-02-15 2011-11-17 Qimonda Ag Verfahren zum Überprüfen einer integrierten elektrischen Schaltung
DE10245037B4 (de) * 2002-09-26 2007-08-23 Infineon Technologies Ag Verfahren zum Entwurf von DRAM-Halbleiter-Speicherbauelementen
US6941527B2 (en) * 2003-04-28 2005-09-06 International Business Machines Corporation Method, system and program product for reducing a size of a configuration database utilized to configure a hardware digital system
US7069534B2 (en) 2003-12-17 2006-06-27 Sahouria Emile Y Mask creation with hierarchy management using cover cells
US7913206B1 (en) 2004-09-16 2011-03-22 Cadence Design Systems, Inc. Method and mechanism for performing partitioning of DRC operations
US7904852B1 (en) 2005-09-12 2011-03-08 Cadence Design Systems, Inc. Method and system for implementing parallel processing of electronic design automation tools
US8448096B1 (en) 2006-06-30 2013-05-21 Cadence Design Systems, Inc. Method and system for parallel processing of IC design layouts
US8214775B2 (en) * 2007-09-14 2012-07-03 Luminescent Technologies, Inc. System for determining repetitive work units
JP2009176049A (ja) * 2008-01-24 2009-08-06 Fujitsu Ltd 解析支援装置、解析支援方法および解析支援プログラム
US20140177940A1 (en) * 2011-08-03 2014-06-26 Hitachi High-Technologies Corporation Recipe generation apparatus, inspection support apparatus, inspection system, and recording media
US20190258396A1 (en) * 2018-02-20 2019-08-22 Adobe Inc. Layout design with adaptive areas
JP7278795B2 (ja) * 2019-02-21 2023-05-22 キヤノン株式会社 画像処理装置、画像処理方法及びプログラム

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Also Published As

Publication number Publication date
EP0721624A4 (Direct) 1996-08-07
EP0721624A1 (en) 1996-07-17
EP0721624B1 (en) 2000-06-14
DE69424944D1 (de) 2000-07-20
WO1995008811A1 (en) 1995-03-30
US5440720A (en) 1995-08-08

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