DE69424745D1 - Schnelle Datenbereitstellung aus physikalisch adressierten Datenspeicherstrukturen mittels Vorhersagemerkmalen von Seitengrenzenüberschreitungen - Google Patents
Schnelle Datenbereitstellung aus physikalisch adressierten Datenspeicherstrukturen mittels Vorhersagemerkmalen von SeitengrenzenüberschreitungenInfo
- Publication number
- DE69424745D1 DE69424745D1 DE69424745T DE69424745T DE69424745D1 DE 69424745 D1 DE69424745 D1 DE 69424745D1 DE 69424745 T DE69424745 T DE 69424745T DE 69424745 T DE69424745 T DE 69424745T DE 69424745 D1 DE69424745 D1 DE 69424745D1
- Authority
- DE
- Germany
- Prior art keywords
- storage structures
- data storage
- predictive features
- page limit
- limit violations
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/655—Same page detection
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Data Mining & Analysis (AREA)
- Databases & Information Systems (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/148,685 US5548739A (en) | 1993-11-04 | 1993-11-04 | Method and apparatus for rapidly retrieving data from a physically addressed data storage structure using address page crossing predictive annotations |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69424745D1 true DE69424745D1 (de) | 2000-07-06 |
DE69424745T2 DE69424745T2 (de) | 2001-02-22 |
Family
ID=22526884
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69424745T Expired - Fee Related DE69424745T2 (de) | 1993-11-04 | 1994-10-20 | Schnelle Datenbereitstellung aus physikalisch adressierten Datenspeicherstrukturen mittels Vorhersagemerkmalen von Seitengrenzenüberschreitungen |
Country Status (5)
Country | Link |
---|---|
US (1) | US5548739A (de) |
EP (1) | EP0652521B1 (de) |
JP (1) | JPH07253927A (de) |
KR (1) | KR100335672B1 (de) |
DE (1) | DE69424745T2 (de) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5732242A (en) | 1995-03-24 | 1998-03-24 | Silicon Graphics, Inc. | Consistently specifying way destinations through prefetching hints |
US5918245A (en) * | 1996-03-13 | 1999-06-29 | Sun Microsystems, Inc. | Microprocessor having a cache memory system using multi-level cache set prediction |
JP3451576B2 (ja) * | 1996-09-20 | 2003-09-29 | 株式会社日立製作所 | 情報処理システム |
US5909698A (en) * | 1997-03-17 | 1999-06-01 | International Business Machines Corporation | Cache block store instruction operations where cache coherency is achieved without writing all the way back to main memory |
US6249853B1 (en) | 1997-06-25 | 2001-06-19 | Micron Electronics, Inc. | GART and PTES defined by configuration registers |
US6282625B1 (en) | 1997-06-25 | 2001-08-28 | Micron Electronics, Inc. | GART and PTES defined by configuration registers |
US6069638A (en) * | 1997-06-25 | 2000-05-30 | Micron Electronics, Inc. | System for accelerated graphics port address remapping interface to main memory |
US6252612B1 (en) | 1997-12-30 | 2001-06-26 | Micron Electronics, Inc. | Accelerated graphics port for multiple memory controller computer system |
US7071946B2 (en) * | 1997-12-30 | 2006-07-04 | Micron Technology, Inc. | Accelerated graphics port for a multiple memory controller computer system |
US6157398A (en) | 1997-12-30 | 2000-12-05 | Micron Technology, Inc. | Method of implementing an accelerated graphics port for a multiple memory controller computer system |
US6349265B1 (en) * | 1999-03-24 | 2002-02-19 | International Business Machines Corporation | Method and apparatus for mapping components of descriptor vectors for molecular complexes to a space that discriminates between groups |
US6519603B1 (en) * | 1999-10-28 | 2003-02-11 | International Business Machine Corporation | Method and system for organizing an annotation structure and for querying data and annotations |
KR101046320B1 (ko) | 2002-05-10 | 2011-07-05 | 인터디지탈 테크날러지 코포레이션 | 무선 링크 제어 재전송을 지원하기 위해 프로토콜 데이터 단위의 재전송의 순위 지정을 하는 시스템 및 방법 |
US9026901B2 (en) * | 2003-06-20 | 2015-05-05 | International Business Machines Corporation | Viewing annotations across multiple applications |
US8321470B2 (en) * | 2003-06-20 | 2012-11-27 | International Business Machines Corporation | Heterogeneous multi-level extendable indexing for general purpose annotation systems |
US7620648B2 (en) * | 2003-06-20 | 2009-11-17 | International Business Machines Corporation | Universal annotation configuration and deployment |
US7870152B2 (en) * | 2003-10-22 | 2011-01-11 | International Business Machines Corporation | Attaching and displaying annotations to changing data views |
US7900133B2 (en) | 2003-12-09 | 2011-03-01 | International Business Machines Corporation | Annotation structure type determination |
US20050210038A1 (en) * | 2004-03-18 | 2005-09-22 | International Business Machines Corporation | Method for providing workflow functionality and tracking in an annotation subsystem |
US7831913B2 (en) * | 2005-07-29 | 2010-11-09 | Microsoft Corporation | Selection-based item tagging |
US7725656B1 (en) * | 2006-10-18 | 2010-05-25 | Guillermo Rozas | Braided set associative caching techniques |
US8195916B2 (en) * | 2009-03-04 | 2012-06-05 | Qualcomm Incorporated | Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode |
US9804969B2 (en) * | 2012-12-20 | 2017-10-31 | Qualcomm Incorporated | Speculative addressing using a virtual address-to-physical address page crossing buffer |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IN165278B (de) * | 1984-09-21 | 1989-09-09 | Digital Equipment Corp | |
IT1202687B (it) * | 1987-03-25 | 1989-02-09 | Honeywell Inf Systems | Memoria tampone a predizione di hit |
IT1216087B (it) * | 1988-03-15 | 1990-02-22 | Honeywell Bull Spa | Sistema di memoria con selezione predittiva di modulo. |
US5099415A (en) * | 1989-02-15 | 1992-03-24 | International Business Machines | Guess mechanism for virtual address translation |
CA2008313A1 (en) * | 1989-05-03 | 1990-11-03 | Howard G. Sachs | Cache accessing method and apparatus |
US5148538A (en) * | 1989-10-20 | 1992-09-15 | International Business Machines Corporation | Translation look ahead based cache access |
US5235697A (en) * | 1990-06-29 | 1993-08-10 | Digital Equipment | Set prediction cache memory system using bits of the main memory address |
AU634354B2 (en) * | 1990-08-31 | 1993-02-18 | Sun Microsystems, Inc. | Method and apparatus for predictive caching |
US5283880A (en) * | 1991-01-02 | 1994-02-01 | Compaq Computer Corp. | Method of fast buffer copying by utilizing a cache memory to accept a page of source buffer contents and then supplying these contents to a target buffer without causing unnecessary wait states |
US5278963A (en) * | 1991-06-21 | 1994-01-11 | International Business Machines Corporation | Pretranslation of virtual addresses prior to page crossing |
US5418922A (en) * | 1992-04-30 | 1995-05-23 | International Business Machines Corporation | History table for set prediction for accessing a set associative cache |
US5361391A (en) * | 1992-06-22 | 1994-11-01 | Sun Microsystems, Inc. | Intelligent cache memory and prefetch method based on CPU data fetching characteristics |
-
1993
- 1993-11-04 US US08/148,685 patent/US5548739A/en not_active Expired - Lifetime
-
1994
- 1994-10-20 DE DE69424745T patent/DE69424745T2/de not_active Expired - Fee Related
- 1994-10-20 EP EP94307724A patent/EP0652521B1/de not_active Expired - Lifetime
- 1994-11-04 JP JP6293677A patent/JPH07253927A/ja active Pending
- 1994-11-04 KR KR1019940028878A patent/KR100335672B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPH07253927A (ja) | 1995-10-03 |
DE69424745T2 (de) | 2001-02-22 |
KR950015130A (ko) | 1995-06-16 |
KR100335672B1 (ko) | 2002-11-27 |
EP0652521B1 (de) | 2000-05-31 |
US5548739A (en) | 1996-08-20 |
EP0652521A1 (de) | 1995-05-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de | ||
8370 | Indication of lapse of patent is to be deleted | ||
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |