DE69422101D1 - Schachbrett-Bildpuffersystem - Google Patents
Schachbrett-BildpuffersystemInfo
- Publication number
- DE69422101D1 DE69422101D1 DE69422101T DE69422101T DE69422101D1 DE 69422101 D1 DE69422101 D1 DE 69422101D1 DE 69422101 T DE69422101 T DE 69422101T DE 69422101 T DE69422101 T DE 69422101T DE 69422101 D1 DE69422101 D1 DE 69422101D1
- Authority
- DE
- Germany
- Prior art keywords
- frame buffer
- buffer system
- checkerboard frame
- checkerboard
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Image Input (AREA)
- Controls And Circuits For Display Device (AREA)
- Storing Facsimile Image Data (AREA)
- Memory System (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/114,552 US5561777A (en) | 1993-08-30 | 1993-08-30 | Process for sequentially reading a page from an image memory in either of two directions |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69422101D1 true DE69422101D1 (de) | 2000-01-20 |
DE69422101T2 DE69422101T2 (de) | 2000-04-27 |
Family
ID=22355959
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69429936T Expired - Fee Related DE69429936T2 (de) | 1993-08-30 | 1994-08-10 | Betriebsverfahren eines Speichers |
DE69422101T Expired - Fee Related DE69422101T2 (de) | 1993-08-30 | 1994-08-10 | Schachbrett-Bildpuffersystem |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69429936T Expired - Fee Related DE69429936T2 (de) | 1993-08-30 | 1994-08-10 | Betriebsverfahren eines Speichers |
Country Status (4)
Country | Link |
---|---|
US (1) | US5561777A (de) |
EP (2) | EP0887802B1 (de) |
JP (1) | JPH07168754A (de) |
DE (2) | DE69429936T2 (de) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2145365C (en) | 1994-03-24 | 1999-04-27 | Anthony M. Jones | Method for accessing banks of dram |
JP3138173B2 (ja) * | 1995-04-10 | 2001-02-26 | シャープ株式会社 | グラフィックス用フレームメモリ装置 |
JPH10283770A (ja) * | 1997-04-07 | 1998-10-23 | Oki Electric Ind Co Ltd | 半導体メモリ装置およびその読み出しおよび書き込み方法 |
US6247084B1 (en) | 1997-10-08 | 2001-06-12 | Lsi Logic Corporation | Integrated circuit with unified memory system and dual bus architecture |
US6016522A (en) * | 1997-11-13 | 2000-01-18 | Creative Labs, Inc. | System for switching between buffers when receiving bursty audio by computing loop jump indicator plus loop start address for read operations in selected buffer |
KR100385370B1 (ko) * | 1998-07-21 | 2003-05-27 | 시게이트 테크놀로지 엘엘씨 | 개선된 메모리 시스템 장치 및 방법 |
US6394850B1 (en) | 2000-03-20 | 2002-05-28 | David Oliphant | Contact pin design for a modular jack |
US6768490B2 (en) * | 2001-02-15 | 2004-07-27 | Sony Corporation | Checkerboard buffer using more than two memory devices |
US6831649B2 (en) * | 2001-02-15 | 2004-12-14 | Sony Corporation | Two-dimensional buffer pages using state addressing |
US6992674B2 (en) * | 2001-02-15 | 2006-01-31 | Sony Corporation | Checkerboard buffer using two-dimensional buffer pages and using state addressing |
US6850241B2 (en) * | 2001-02-15 | 2005-02-01 | Sony Corporation | Swapped pixel pages |
US7088369B2 (en) * | 2001-02-15 | 2006-08-08 | Sony Corporation | Checkerboard buffer using two-dimensional buffer pages and using bit-field addressing |
US6791557B2 (en) * | 2001-02-15 | 2004-09-14 | Sony Corporation | Two-dimensional buffer pages using bit-field addressing |
US6765579B2 (en) * | 2001-02-15 | 2004-07-20 | Sony Corporation | Pixel pages using combined addressing |
US6831651B2 (en) * | 2001-02-15 | 2004-12-14 | Sony Corporation | Checkerboard buffer |
US6801204B2 (en) * | 2001-02-15 | 2004-10-05 | Sony Corporation, A Japanese Corporation | Checkerboard buffer using memory blocks |
US6828977B2 (en) * | 2001-02-15 | 2004-12-07 | Sony Corporation | Dynamic buffer pages |
US7038691B2 (en) * | 2001-02-15 | 2006-05-02 | Sony Corporation | Two-dimensional buffer pages using memory bank alternation |
US7379069B2 (en) * | 2001-02-15 | 2008-05-27 | Sony Corporation | Checkerboard buffer using two-dimensional buffer pages |
US6765580B2 (en) * | 2001-02-15 | 2004-07-20 | Sony Corporation | Pixel pages optimized for GLV |
US6803917B2 (en) * | 2001-02-15 | 2004-10-12 | Sony Corporation | Checkerboard buffer using memory bank alternation |
US7205993B2 (en) * | 2001-02-15 | 2007-04-17 | Sony Corporation | Checkerboard buffer using two-dimensional buffer pages and using memory bank alternation |
US6795079B2 (en) * | 2001-02-15 | 2004-09-21 | Sony Corporation | Two-dimensional buffer pages |
US6831650B2 (en) * | 2001-02-15 | 2004-12-14 | Sony Corporation | Checkerboard buffer using sequential memory locations |
US20030058368A1 (en) * | 2001-09-24 | 2003-03-27 | Mark Champion | Image warping using pixel pages |
US6965980B2 (en) * | 2002-02-14 | 2005-11-15 | Sony Corporation | Multi-sequence burst accessing for SDRAM |
US6992707B2 (en) * | 2002-03-06 | 2006-01-31 | Hewlett-Packard Development Company, L.P. | Delayed encoding based joint video and still image pipeline with still burst mode |
US6919902B2 (en) * | 2002-06-03 | 2005-07-19 | Seiko Epson Corporation | Method and apparatus for fetching pixel data from memory |
US7034887B2 (en) * | 2002-07-15 | 2006-04-25 | Seiko Epson Corporation | Method and apparatus for flicker filtering interlaced display data |
US7583732B2 (en) * | 2002-12-06 | 2009-09-01 | Broadcom Corporation | Managing bursts of data |
KR100612414B1 (ko) * | 2003-04-28 | 2006-08-16 | 삼성전자주식회사 | 영상 데이터 처리 시스템 및 영상 데이터 독출/기입 방법 |
US7111093B2 (en) * | 2003-06-23 | 2006-09-19 | Intel Corporation | Ping-pong buffer system having a buffer to store a subset of data from a data source |
FR2951310B1 (fr) * | 2009-10-13 | 2011-11-18 | St Microelectronics Rousset | Dispositif de memoire a protocole serie et procede d'adressage correspondant |
US8564603B2 (en) * | 2010-10-24 | 2013-10-22 | Himax Technologies Limited | Apparatus for controlling memory device and related method |
CN106201363B (zh) * | 2016-07-26 | 2023-01-31 | 四川大学 | 视频流像素级数据随机实时访问的存储器及存储方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4247920A (en) * | 1979-04-24 | 1981-01-27 | Tektronix, Inc. | Memory access system |
JPS56140390A (en) * | 1980-04-04 | 1981-11-02 | Nippon Electric Co | Picture memory |
DE3015125A1 (de) * | 1980-04-19 | 1981-10-22 | Ibm Deutschland Gmbh, 7000 Stuttgart | Einrichtung zur speicherung und darstellung graphischer information |
US4740927A (en) * | 1985-02-13 | 1988-04-26 | International Business Machines Corporation | Bit addressable multidimensional array |
US4818932A (en) * | 1986-09-25 | 1989-04-04 | Tektronix, Inc. | Concurrent memory access system |
US4893257A (en) * | 1986-11-10 | 1990-01-09 | International Business Machines Corporation | Multidirectional scan and print capability |
KR900000114B1 (ko) * | 1986-12-29 | 1990-01-20 | 박종원 | 영상처리용 메모리시스템 |
JPH01291387A (ja) * | 1988-05-19 | 1989-11-22 | Hitachi Ltd | 画像処理装置 |
DE3913599C1 (en) * | 1989-04-25 | 1990-01-18 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung Ev, 8000 Muenchen, De | Intermediate image store e.g. for TV transmission - assigns separate control to each video channel for connection to all memory blocks |
US5361339A (en) * | 1992-05-04 | 1994-11-01 | Xerox Corporation | Circuit for fast page mode addressing of a RAM with multiplexed row and column address lines |
-
1993
- 1993-08-30 US US08/114,552 patent/US5561777A/en not_active Expired - Fee Related
-
1994
- 1994-08-10 DE DE69429936T patent/DE69429936T2/de not_active Expired - Fee Related
- 1994-08-10 EP EP98114329A patent/EP0887802B1/de not_active Expired - Lifetime
- 1994-08-10 DE DE69422101T patent/DE69422101T2/de not_active Expired - Fee Related
- 1994-08-10 EP EP94305916A patent/EP0640979B1/de not_active Expired - Lifetime
- 1994-08-26 JP JP6201787A patent/JPH07168754A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
DE69429936T2 (de) | 2002-06-20 |
US5561777A (en) | 1996-10-01 |
JPH07168754A (ja) | 1995-07-04 |
DE69429936D1 (de) | 2002-03-28 |
DE69422101T2 (de) | 2000-04-27 |
EP0640979B1 (de) | 1999-12-15 |
EP0640979A3 (de) | 1995-08-09 |
EP0887802A3 (de) | 1999-02-10 |
EP0887802B1 (de) | 2002-02-20 |
EP0887802A2 (de) | 1998-12-30 |
EP0640979A2 (de) | 1995-03-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |