DE69421340D1 - Kohärenter Datenaustausch, Verwaltungsverfahren zwischen den Stufen einer mindestens dreistufigen Speicherhierarchie - Google Patents

Kohärenter Datenaustausch, Verwaltungsverfahren zwischen den Stufen einer mindestens dreistufigen Speicherhierarchie

Info

Publication number
DE69421340D1
DE69421340D1 DE69421340T DE69421340T DE69421340D1 DE 69421340 D1 DE69421340 D1 DE 69421340D1 DE 69421340 T DE69421340 T DE 69421340T DE 69421340 T DE69421340 T DE 69421340T DE 69421340 D1 DE69421340 D1 DE 69421340D1
Authority
DE
Germany
Prior art keywords
levels
data exchange
level storage
storage hierarchy
coherent data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69421340T
Other languages
English (en)
Other versions
DE69421340T2 (de
Inventor
Sylvie Lesmanne
Anne Kaszynski
Alain Boudou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SAS
Original Assignee
Bull SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SAS filed Critical Bull SAS
Publication of DE69421340D1 publication Critical patent/DE69421340D1/de
Application granted granted Critical
Publication of DE69421340T2 publication Critical patent/DE69421340T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69421340T 1993-07-15 1994-07-11 Kohärenter Datenaustausch, Verwaltungsverfahren zwischen den Stufen einer mindestens dreistufigen Speicherhierarchie Expired - Lifetime DE69421340T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9308711A FR2707774B1 (fr) 1993-07-15 1993-07-15 Procédé de gestion cohérente des échanges entre des niveaux d'une hiérarchie de mémoires à au moins trois niveaux.

Publications (2)

Publication Number Publication Date
DE69421340D1 true DE69421340D1 (de) 1999-12-02
DE69421340T2 DE69421340T2 (de) 2000-02-10

Family

ID=9449277

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69421340T Expired - Lifetime DE69421340T2 (de) 1993-07-15 1994-07-11 Kohärenter Datenaustausch, Verwaltungsverfahren zwischen den Stufen einer mindestens dreistufigen Speicherhierarchie

Country Status (5)

Country Link
US (1) US5568633A (de)
EP (1) EP0636988B1 (de)
JP (1) JPH07152646A (de)
DE (1) DE69421340T2 (de)
FR (1) FR2707774B1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6078337A (en) * 1994-09-12 2000-06-20 Canon Kabushiki Kaisha Maintaining consistency of cache memory data by arbitrating use of a connection route by plural nodes
JP3872118B2 (ja) * 1995-03-20 2007-01-24 富士通株式会社 キャッシュコヒーレンス装置
US5860120A (en) * 1996-12-09 1999-01-12 Intel Corporation Directory-based coherency system using two bits to maintain coherency on a dual ported memory system
US6092156A (en) * 1997-11-05 2000-07-18 Unisys Corporation System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations
ATE258698T1 (de) * 1997-11-05 2004-02-15 Unisys Corp Auf verzeichnis basierendes cache-speicher- kohärenz-system
US6052760A (en) * 1997-11-05 2000-04-18 Unisys Corporation Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks
US6049845A (en) * 1997-11-05 2000-04-11 Unisys Corporation System and method for providing speculative arbitration for transferring data
US6314501B1 (en) 1998-07-23 2001-11-06 Unisys Corporation Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory
US6338117B1 (en) * 1998-08-28 2002-01-08 International Business Machines Corporation System and method for coordinated hierarchical caching and cache replacement
US6665761B1 (en) 1999-07-28 2003-12-16 Unisys Corporation Method and apparatus for routing interrupts in a clustered multiprocessor system
US6687818B1 (en) 1999-07-28 2004-02-03 Unisys Corporation Method and apparatus for initiating execution of an application processor in a clustered multiprocessor system
US6338116B1 (en) * 1999-11-09 2002-01-08 International Business Machines Corporation Method and apparatus for a data-less write operation within a cache memory hierarchy for a data processing system
JP2001166993A (ja) * 1999-12-13 2001-06-22 Hitachi Ltd 記憶制御装置およびキャッシュメモリの制御方法
EP1227385A3 (de) * 2001-01-24 2005-11-23 Matsushita Electric Industrial Co., Ltd. Integrierte Halbleiterschaltung
JP2003345528A (ja) * 2002-05-22 2003-12-05 Hitachi Ltd 記憶システム
JP4090400B2 (ja) * 2003-07-24 2008-05-28 株式会社日立製作所 ストレージシステム
JP4408692B2 (ja) * 2003-12-19 2010-02-03 富士通株式会社 通信装置管理プログラム

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4445174A (en) * 1981-03-31 1984-04-24 International Business Machines Corporation Multiprocessing system including a shared cache
JPS61290550A (ja) * 1985-06-19 1986-12-20 Hitachi Ltd 階層記憶制御方式
JP2552704B2 (ja) * 1988-03-08 1996-11-13 富士通株式会社 データ処理装置
JPH0680499B2 (ja) * 1989-01-13 1994-10-12 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプロセッサ・システムのキャッシュ制御システムおよび方法
JPH0721781B2 (ja) * 1989-03-13 1995-03-08 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプロセツサ・システム
JPH02253356A (ja) * 1989-03-28 1990-10-12 Toshiba Corp 階層キャッシュメモリ装置とその制御方式
JPH03172943A (ja) * 1989-12-01 1991-07-26 Mitsubishi Electric Corp キャッシュメモリ制御方式
US5136700A (en) * 1989-12-22 1992-08-04 Digital Equipment Corporation Apparatus and method for reducing interference in two-level cache memories
JPH061463B2 (ja) * 1990-01-16 1994-01-05 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプロセッサ・システムおよびそのプライベート・キャッシュ制御方法
JPH03230238A (ja) * 1990-02-05 1991-10-14 Nippon Telegr & Teleph Corp <Ntt> キャッシュメモリ制御方式
JPH0625984B2 (ja) * 1990-02-20 1994-04-06 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン マルチプロセツサ・システム
JPH04357541A (ja) * 1990-07-27 1992-12-10 Fujitsu Ltd 階層メモリ制御方式
US5291442A (en) * 1990-10-31 1994-03-01 International Business Machines Corporation Method and apparatus for dynamic cache line sectoring in multiprocessor systems
JPH04191946A (ja) * 1990-11-27 1992-07-10 Agency Of Ind Science & Technol スヌープキャッシュメモリ制御方式
CA2051209C (en) * 1990-11-30 1996-05-07 Pradeep S. Sindhu Consistency protocols for shared memory multiprocessors

Also Published As

Publication number Publication date
FR2707774B1 (fr) 1995-08-18
EP0636988A1 (de) 1995-02-01
JPH07152646A (ja) 1995-06-16
US5568633A (en) 1996-10-22
FR2707774A1 (fr) 1995-01-20
EP0636988B1 (de) 1999-10-27
DE69421340T2 (de) 2000-02-10

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Legal Events

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