DE69420233T2 - Einrichtung zum Berechnen von Paritätsbits in Verbindung mit einer Summe zweier Zahlen - Google Patents

Einrichtung zum Berechnen von Paritätsbits in Verbindung mit einer Summe zweier Zahlen

Info

Publication number
DE69420233T2
DE69420233T2 DE69420233T DE69420233T DE69420233T2 DE 69420233 T2 DE69420233 T2 DE 69420233T2 DE 69420233 T DE69420233 T DE 69420233T DE 69420233 T DE69420233 T DE 69420233T DE 69420233 T2 DE69420233 T2 DE 69420233T2
Authority
DE
Germany
Prior art keywords
sum
numbers
connection
parity bits
calculating parity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69420233T
Other languages
English (en)
Other versions
DE69420233D1 (de
Inventor
Michel Thill
Pascal Delamotte
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull Sa Les Clayes Sous Bois Fr
Original Assignee
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SA filed Critical Bull SA
Application granted granted Critical
Publication of DE69420233D1 publication Critical patent/DE69420233D1/de
Publication of DE69420233T2 publication Critical patent/DE69420233T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/098—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit using single parity bit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/506—Indexing scheme relating to groups G06F7/506 - G06F7/508
    • G06F2207/5063—2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)
DE69420233T 1993-11-30 1994-11-24 Einrichtung zum Berechnen von Paritätsbits in Verbindung mit einer Summe zweier Zahlen Expired - Lifetime DE69420233T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9314287A FR2713364B1 (fr) 1993-11-30 1993-11-30 Dispositif de calcul des bits de parité associés à une somme de deux nombres.

Publications (2)

Publication Number Publication Date
DE69420233D1 DE69420233D1 (de) 1999-09-30
DE69420233T2 true DE69420233T2 (de) 1999-12-30

Family

ID=9453351

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69420233T Expired - Lifetime DE69420233T2 (de) 1993-11-30 1994-11-24 Einrichtung zum Berechnen von Paritätsbits in Verbindung mit einer Summe zweier Zahlen

Country Status (5)

Country Link
US (1) US5689451A (de)
EP (1) EP0655685B1 (de)
JP (1) JP2592584B2 (de)
DE (1) DE69420233T2 (de)
FR (1) FR2713364B1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4485577B2 (ja) * 2006-02-01 2010-06-23 富士通株式会社 パリティ生成回路，パリティ生成回路用構成回路，情報処理装置，及びエンコーダ
DE102007012726A1 (de) 2007-03-16 2008-09-18 Micronas Gmbh Verschlüsselungsvorrichtung mit einem mehrstufigen Verschlüsselungsblock

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3925647A (en) * 1974-09-30 1975-12-09 Honeywell Inf Systems Parity predicting and checking logic for carry look-ahead binary adder
US4224680A (en) 1978-06-05 1980-09-23 Fujitsu Limited Parity prediction circuit for adder/counter
US4879675A (en) * 1988-02-17 1989-11-07 International Business Machines Corporation Parity generator circuit and method
FR2627605B1 (fr) * 1988-02-18 1990-06-15 Bull Sa Dispositif pour le calcul des bits de parite d'une somme de deux nombres
US4924423A (en) * 1988-04-25 1990-05-08 International Business Machines Corporation High speed parity prediction for binary adders using irregular grouping scheme

Also Published As

Publication number Publication date
EP0655685B1 (de) 1999-08-25
DE69420233D1 (de) 1999-09-30
FR2713364B1 (fr) 1996-01-12
JP2592584B2 (ja) 1997-03-19
FR2713364A1 (fr) 1995-06-09
JPH07200331A (ja) 1995-08-04
EP0655685A1 (de) 1995-05-31
US5689451A (en) 1997-11-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: BULL S.A., LES CLAYES SOUS BOIS, FR