DE69412670D1 - Vorrichtung zur Unterdrückung von falschen Flanken in einem Eingangssignal - Google Patents

Vorrichtung zur Unterdrückung von falschen Flanken in einem Eingangssignal

Info

Publication number
DE69412670D1
DE69412670D1 DE69412670T DE69412670T DE69412670D1 DE 69412670 D1 DE69412670 D1 DE 69412670D1 DE 69412670 T DE69412670 T DE 69412670T DE 69412670 T DE69412670 T DE 69412670T DE 69412670 D1 DE69412670 D1 DE 69412670D1
Authority
DE
Germany
Prior art keywords
input signal
false edges
suppressing false
suppressing
edges
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69412670T
Other languages
German (de)
English (en)
Inventor
Alan C Folmsbee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69412670D1 publication Critical patent/DE69412670D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Noise Elimination (AREA)
DE69412670T 1993-03-10 1994-03-07 Vorrichtung zur Unterdrückung von falschen Flanken in einem Eingangssignal Expired - Lifetime DE69412670D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US2884993A 1993-03-10 1993-03-10

Publications (1)

Publication Number Publication Date
DE69412670D1 true DE69412670D1 (de) 1998-10-01

Family

ID=21845823

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69412670T Expired - Lifetime DE69412670D1 (de) 1993-03-10 1994-03-07 Vorrichtung zur Unterdrückung von falschen Flanken in einem Eingangssignal

Country Status (6)

Country Link
US (1) US6366160B1 (enExample)
EP (1) EP0615341B1 (enExample)
JP (1) JPH06326569A (enExample)
KR (1) KR940023022A (enExample)
DE (1) DE69412670D1 (enExample)
TW (1) TW278280B (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0845862A3 (en) * 1996-11-30 2000-02-23 Daewoo Electronics Co., Ltd Circuit for removing noise components of oscillator
FR2810171B1 (fr) * 2000-06-09 2004-04-16 Mhs Dispositif de filtrage et de calibrage d'une impulsion d'entree par rapport a une duree de reference
CN118054783B (zh) * 2024-04-16 2024-06-21 瓴科微(上海)集成电路有限责任公司 一种边沿检测自动增强电平转换电路

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55156421A (en) * 1979-05-23 1980-12-05 Fujitsu Ltd Pulse-width reproducing circuit
US4730131A (en) * 1985-01-28 1988-03-08 General Electric Company Input signal conditioning circuit
US4894791A (en) * 1986-02-10 1990-01-16 Dallas Semiconductor Corporation Delay circuit for a monolithic integrated circuit and method for adjusting delay of same
JPH0681018B2 (ja) * 1986-03-31 1994-10-12 三菱電機株式会社 半導体集積回路
US5068553A (en) * 1988-10-31 1991-11-26 Texas Instruments Incorporated Delay stage with reduced Vdd dependence
US5028824A (en) * 1989-05-05 1991-07-02 Harris Corporation Programmable delay circuit
JPH03127508A (ja) * 1989-10-12 1991-05-30 Nec Corp Ｃｍｏｓ遅延回路
JPH04172711A (ja) * 1990-11-06 1992-06-19 Mitsubishi Electric Corp 半導体遅延回路
US5113098A (en) * 1991-03-29 1992-05-12 Advanced Micro Devices, Inc. Glitch remover circuit for transmission links
JP3127508B2 (ja) 1991-09-09 2001-01-29 富士ゼロックス株式会社 インクジェット記録ヘッド、並びにそのヘッド前端面溌液膜形成方法、およびヘッド前端面溌液膜形成装置
US5530400A (en) * 1991-11-29 1996-06-25 General Instruments Corp. Transistor circuit with transistor characteristic sensor
JPH05175799A (ja) * 1991-12-24 1993-07-13 Nissan Motor Co Ltd 雑音除去回路
JP3550404B2 (ja) * 1992-09-10 2004-08-04 株式会社日立製作所 可変遅延回路及び可変遅延回路を用いたクロック信号供給装置

Also Published As

Publication number Publication date
EP0615341B1 (en) 1998-08-26
EP0615341A1 (en) 1994-09-14
TW278280B (enExample) 1996-06-11
JPH06326569A (ja) 1994-11-25
KR940023022A (ko) 1994-10-22
US6366160B1 (en) 2002-04-02

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Legal Events

Date Code Title Description
8332 No legal effect for de