DE69401478T2 - Circuit for generating deflection signals with generator of periodic signals - Google Patents

Description

The present invention relates to a circuit for producing deflection signals with a generator for periodic signals with any period but a given shape. Its application is in the field of television. It is preferably used to correct a horizontal deflection. The invention is described in relation to the production of a digital signal which is also converted into analogue form at the output of the processing. However, the signal could directly be an analogue signal processed according to the principles of the invention. It could also remain a digital signal. The invention also aims at the application of a method as described below.

The invention is described in the context of the processing of television signals. In television signals for displaying images on cathode ray tubes, horizontal deflection signals are known, as are vertical deflection signals. The horizontal deflection signal is a signal that is sent to the electrodes or coils for deflecting one or more electron beams from the guns that project the electrons of a cathode onto an electroluminescent screen. To produce an image, deflection is therefore effected across the screen to form a certain number of consecutive lines, one below the other and continuing from top to bottom across the screen.

Depending on the solution found, as well as on the visualization standards used in different countries of the world, the number of lines displayed on the screen varies. Currently, we know of images with 420 lines or 625 lines, while the new standards provide for 1024 lines or even 2048 lines. In addition, the refresh rate of the images on the screen is 25 images per second and also depends on the standards and the desired quality. In particular, the aim is to achieve 50 images per second to avoid scintillating effects.

The different standards and the different needs therefore lead to special deflection signal generators for each application.

Furthermore, any visualization using a cathode ray tube encounters a problem in the representation of the image. This representation is in fact only in a distorted form: the distortion is a pincushion-shaped deformation. The pincushion-shaped deformation has the disadvantage for horizontal deflection that the deflection length for the trajectory of the electron onto the screen, the spot, is not the same at every height of the line to be deflected on the screen. In practice, the length traversed by the spot is greater for the lower and upper lines than for the middle lines. The difference is in fact continuous, so that the image displayed has profiles in the shape of a parabola on its right and left edges.

This phenomenon is based on the fact that identical signals are applied to the deflection elements for the electron guns, whatever the deflected line. This phenomenon is already known and has already been corrected by applying a additional voltage or a deflection current has been applied so that the usable area is always the same, whatever the height of the line. For example, the TDA 815 circuit from SGS THOMSON MICROELECTRONICS is suitable for generating the necessary correction signals. However, the use of a circuit of this type requires that it be controlled in advance, in particular according to a standard in which the display monitor can be corrected, and on the other hand according to the display monitor's own variations. This leads to devices in which the mode of use, the standards, must be known in advance.

The invention was based on the idea of being independent of a priori determination and of allowing future adaptation to any standard that is possible. The problem to be solved in this case is therefore, knowing the deformation curve of the cushion shape that is inherent in a visualization monitor, i.e. the shape of the parabolas on the right (and left) when the image displayed is distorted, to generate a signal (in this case a correction signal) that develops over a chosen interval in the time between a starting value and an arrival value, even though the duration of this chosen interval is not known a priori. This is particularly the case when the standard is raised from 25 frames per second to 50 or 40 frames per second.

The aim is therefore to create a system that allows this time to be extended or shortened. To date, only analog circuits exist that allow such changes. Moreover, these analog circuits are limited to generating very simple signals: essentially sinusoidal. In analog circuits, it is sufficient to modify a reactive parameter, a capacitance or an adjustable coil acting on the frequency, to produce the desired result.

According to the invention, however, it is intended to be able to modify signals of any shape, not necessarily sinusoidal, of course. This aim is achieved by the invention by counting, during the interval to be observed, the pulses emitted by a clock generator that is fast enough to generate many pulses during this interval. After counting, during a first interval to be observed, a number A of pulses is obtained that depends on the frequency of this clock generator and the duration of this interval. This number of pulses is then divided by an integer 2N to obtain a number P of pulses that corresponds to a multiple of a part of the total number of pulses. The pulses generated by this clock generator are then counted to generate trains or packets of pulses, so that the number P of these pulses in the trains corresponds exactly to a multiple of this part. Each time a sequence has been completely counted, a value is read from a random access memory whose address corresponds to the rank of the sequence in the interval. The value read from this memory can be arbitrary, but according to a rank of a sequence that occurs repeatedly, it is read periodically, as are the preceding and subsequent ones, at the preceding and subsequent addresses in this memory. In practice, the rank is implemented by the state of a counter that counts the number of the sequence of counted pulses. Such a sequence of values read from the memory recreates the periodic signal sought.

A circuit of this type is described in GB-A-1 353 147. However, it has the disadvantage that it only meets one standard. In "Fernsehtechnik ohne Ballast" by O. LIMANN et al., 1991, Franzis, Munich, Germany; pages 498-523, the need to adapt the circuits for producing deflection signals to television screens with different standards is highlighted. However, this knowledge is not sufficient for adaptation to future standards, where the definitions are not yet known at the moment the monitor is completed.

The invention therefore aims to provide a circuit for generating deflection signals for television monitors equipped with a generator for periodic signals of a predetermined shape, comprising:

- a clock generator for outputting a number A of pulses during a selected duration for the periodic signals, where A is less than or equal to 2N+M, where N and M are integers,

- a first numerical binary counter for counting a sequence of P pulses from the clock generator with M-bit counting width, where 2M is greater than or equal to P, which receives the clock generator pulses via its counting input, the P pulses from the clock generator occurring during 1/(2N) fractions of the said selected duration, and which outputs a sequence signal at each counting sequence,

- a second numerical binary counter with N-bit cycle, which reads the said sequence signal via its counting input and outputs an address signal each time a sequence signal is counted,

- a memory with at least 2N addresses that can be accessed at will, which is provided with an address input and a data output, which is connected via its address input to the output of the second counter and outputs binary signals via its output that correspond to the generated address signals, and

- a converter circuit connected to the output of the memory to generate the said periodic signal in dependence on the received binary signals,

and otherwise with the features specified in claim 1.

The invention is made clear in the following description and by means of the figures that are attached. These are given only as an example, without limiting the invention. The figures show:

- Figure 1: a circuit for counting the pulses generated by a clock during a selected duration. This circuit also comprises a device for dividing the number of pulses counted in order to generate a reduced number of pulses corresponding to those contained in a train of pulses;

- Figure 2: a circuit for implementing the invention in an application for correcting the pincushion-shaped deformation on a television screen;

- Figure 3: a flow chart executed by a control circuit for the circuits in Figures 1 and 2 ;

- Figure 4: a schematic representation of a microprocessor circuit suitable for implementing the invention.

Figure 2 shows a generator of periodic signals according to the invention with any period but a given shape. This circuit comprises a clock 1 which emits a large number of pulses during a duration chosen for the periodic signals. For example, in an application for correcting the pincushion distortion of a display screen, the periodic signal for deflecting the raster is of the order of 25 milliseconds (for 40 frames per second). By choosing a clock 1 of 4 MHz, it is possible to obtain up to 100,000 pulses per raster. Here, a raster is considered to be equivalent to an image and therefore to two half-rasters. The generator also comprises a first binary numerical counter 2 with M cascaded cells. In an example, M is 9. Counter 2 is a binary counter which performs a natural binary count. However, it can also be a bit-by-bit counter. Counter 2 has M outputs that output binary signals that represent the state of the M cells of this counter. Counter 2 is in practice a down counter that is charged with the contents of a register 3 (the same number of bits) before counting. Once counter 2 is charged, it counts down its contents in the sequence of pulses from clock 1 until a state of zero is reached. The content of the counter is P, where P is less than or equal to 2M.

The zero state can be represented schematically by way of example by providing a gate 4 of the NOR type with M inputs connected to the M outputs or states of the counter. The output of this gate 4 temporarily passes through the state 1 when the M outputs of the counter 2 are at zero. The output of the gate 4 is itself used to load the counter 2 with the contents of the register 3. In other words, for each operation of counting a sequence of pulses whose number corresponds to the value loaded in the register 3, the subtraction is repeated. Consequently, the NOR gate 4 delivers a pulse as soon as the sequence has been counted. This count pulse of the sequence is then transmitted to a second counter 5, which is an N counter with N cells. N is 8, for example. The counter 5 counts in natural binary counting sequence. Each time the counter 5 receives a pulse, it delivers a counting word with N bits, which corresponds to an address, to its N counting outputs. This counting word is applied to the address input of a random access memory 6. With the above-mentioned addressing, the memory 6 delivers a binary word, which corresponds to a binary signal.

This binary signal is applied, in the particularly described application of the present invention, to the magnetic coils for horizontal deflection 7 of a cathode ray monitor 8. The coils 7 effect the horizontal deflection. When a constant current flows through the coils 7, they provide a deflection for a predetermined duration, the length of which depends on the height of the scanned line on the screen.

This clearly shows why this deflection is equivalent to a deflection angle. If we assume that the cathode 9 of the cathode screen 8 is very close to the screen itself, there is a much greater path between this screen, designated 10, and the cathode 9 for the lines at the bottom and at the top of the screen than for the middle lines. Consequently, for the same angle (or the same half-angle) for a given deflection, the greater the path traversed, the greater the deviation of the spot. The result of this phenomenon is that the length of the deflected lines, depending on their height on the screen, is essentially reflected in the contours drawn by the parabolic arcs 11 and 12 on the screen 10.

In the present case, the invention recognized that the unchanged type is essentially based on the geometry of the screen (the distance between screen 10 and cathode 9). This has nothing to do with the deflection mode itself, i.e. whether 400 lines per image, 625 or even whether 25 or 50 images per second are displayed.

The signal processed at the output of the memory 6 by a D/A converter 13 is in practice superimposed on the usual deflection signal applied to the coils 7. This superposition is well known. It is represented schematically by the power supply 14 of the coils 7, the intensity produced being dependent on the value output by the A/D converter 13. Assuming that for the central lines the normally deflected distance is smaller than the useful distance, the current that must flow through the coils 7 must be increased again. In fact, another correction circuit must be provided in addition: this serves to shift the point of beginning of the deflection on one side, on the side where to deflect the line. These effects are neglected here, since the only important thing for the invention is to generate the periodic signal itself. The circuits in the device 8 are already able to carry out adequate corrections once they have received the command for the correction signals.

The invention therefore involves measuring an unknown duration: this duration is that corresponding to a frame of the received video signal. This measure is then taken into account when correcting the deflection signals in a periodic signal with a duration thus measured.

In the invention, it was also decided to distribute the correction to be applied to the screen in discrete steps with a reduced number of steps. This number of steps is preferably chosen so that it is less than the smallest number of lines that the television screen can display. Given that 400 lines is currently the minimum, a correction of 256 steps was chosen. In other words, for a given duration (but unknown and measured) for deflecting a raster, it was decided to divide this duration into 256 elementary sub-intervals. For each of these sub-intervals, which are of course arranged one after the other while maintaining their temporal order, it is possible to adapt a line or a group of lines for horizontal deflection so that one is adjacent to the other on the screen 10. Consequently, the line or lines must receive the same correction. This is the aim of the signal generated by the memory 6. Every time you change the line or group of lines, the content of counter 5 is changed. The cycle starts anew in each interval.

There is a direct relationship between the specific choice of N = 8 and the number of steps 256, since one has decided to divide the interval into 256 subintervals. In fact, 28 = 256.

For this purpose, the output of the memory 6 is not directly connected to the A/D converter 13, but is connected to a register 15 which stores a correction value for the entire duration of a subinterval corresponding to a line or group of lines. Under these conditions, a horizontal synchronization signal HSYNC is applied to the register 15 in order to subtract in the register a value which must be transmitted each time by the converter 13. The signal HSYNC is also applied to the converter 13 to start the conversion. Every time the deflection reaches the beginning of the line, the register 15 is read. As soon as a group of lines has been displayed on the screen 10, the counter/down counter 2 outputs a bit, the counter 5 changes state by counting this bit, the memory 6 is addressed to another address and the register 15 is loaded with another value. Under these conditions, at the start of the following line, the content of the register 15 is no longer the same. The converter 13 then converts the new value. In this way, a stepped profile is obtained to compensate for the contour effects 11 and 12. In the case where N = 8 and where 400 lines are to be displayed, the groups of lines will not always be identical, sometimes they will comprise two lines, sometimes one line. The periodic signal from the memory 6 naturally develops according to the intervals generated. The adaptation to the number of lines to be displayed is carried out automatically by subtracting the HSYNC signals from the contents of the memory 15.

The circuit in Figure 2 is the circuit according to the invention which activates the generator for periodic signals.

Figure 1 is used to explain how the contents of register 3 are generated. To simplify the explanation, we will assume that counters 2 and 5 are organized differently. Counter 5 is now placed above counter 2. It receives the signal from clock 1 at its input and causes counter 2 to count a unit each time its highest bit changes state. If we consider what happens when this counting is carried out during a given (but unknown) interval, we will see that when counting begins, the counter is loaded with a digit equal to the number of revolutions of counter 5. In practice, since counter 5 is an 8-bit counter, it counts 256 pulses per revolution. At the start of the measurement, counter 2 is stored with the number of pulses required per sequence to have 256 sequences in a given interval. To limit the counting to what happens during a single interval, the flip-flop D 16 is used to reset inputs 17 and 18 of counters 5 and 2. Flip-flop 16 receives the signal from clock 1 and a signal at the end of the frame VFback. Each time a whole image is viewed, flip-flop D 16 receives the signal VFback and changes state in a pulsed manner. Under these conditions, counter 5 and counter 2 can be reset to zero. The signal at the end of the frame VFback is also used to load the contents of a register 3 with the state of counter 2 at the moment when this return of the frame occurs. Counter 2 is a 9-bit counter, which Register 3 is a register with at least 9 flip-flops for writing the contents of bits 1 to 9 of counter 2.

In a particularly interesting variant, a precision slightly greater than the measured duration of the given interval was achieved. In fact, it is entirely possible that the unknown interval to be measured does not correspond to an exact digit of a sequence of 256 pulses from clock 1 at 4 MHz. In particular, it is possible that, in the worst case, an error of 128 pulses could be generated in this way, since this duration corresponds to an integer multiple of 256 pulses plus 128 pulses. To take this into account, in a way that will be explained below, the state partially counted by counter 5, before it reaches zero, is loaded with an upper bit of counter 5 at the moment of the return of the grid, by means of an additional flip-flop of register 3. This flip-flop is called the flip-flop of bit 0. The state of this bit 0 is used at the input of an AND gate 19, Figure 2, whose output is used to enable transmission in an order determined by a flip-flop 20. The idea is therefore that in this case the sequences are no longer always counted with P pulses, but on the contrary, to count P pulses once and P+1 pulses once. To do this, every other time the change in state of counter 5 is triggered one pulse later than at the beginning of the period, thus ending the counting of P pulses (P is the binary content of register 3 with M (M = 9) bits). In this case, instead of P, P+1 is counted. Thus, one more bit is counted 128 times out of 256 possibilities. Under these conditions, the recharging of counter 2 with the content of register 3 is carried out at the moment the delivered signal is transmitted to counter 5 by a multiplexer 21.

In this way, a correction is achieved in the correction itself as if no shift or distortion took place. If this type of correction were not made, there would be a shift, not necessarily disturbing but nonetheless visible in the parabolic correction.

For this purpose, the flip-flop 20 is a bistable type circuit and receives the signal delivered by the gate 4. It changes state every other time, if the high bit of the counter 5 has the value 1 at the time of detection. Consequently, the AND gate 19 changes state every other time. The AND gate 19 controls a multiplexer 21 which receives at its input the signal delivered by the gate 4, on the one hand directly and on the other hand transmitted by a flip-flop of the D type 22. The flip-flop D 22 receives the clock signal, also at 4 MHz. The flip-flop D 22 also receives at its input the signal delivered by the gate 4. The flip-flop D 22 transmits at its output the signal available at the gate 4 after a clock pulse has arrived at its clock input. This corresponds exactly to counting an additional clock pulse, since in practice this flip-flop D slows down the transmission of the counting of the 2N addresses.

The gate 19 therefore controls the multiplexer 21 in such a way that it directly transmits the signal output by the gate 4 to the counter 5 or the signal from the flip-flop D 22. If, however, the highest bit of the counter 5 at the moment of recording, Figure 1, is not 1 but 0, the gate 19 permanently delivers 0 at the output. In this case, the multiplexer 21 permanently connects the output of the gate 4 directly to the input of the counter 5.

Preferably, the counter 5 is itself reset to zero at the moment of the change of the grid by receiving the signal VFback at its reset to zero input.

Figure 3 shows the operation of the invention. At the beginning, during a first phase, the contents of register 3 measured by counter 2 are recorded. The duration of this first phase corresponds, for example, to a raster. Then, we wait to receive an interval signal. In this case, it is a raster signal: VFback. When this is received, the counters are set to zero using flip-flop 16. Then, we start counting until the interval signal is received a second time. During this sequence, counter 5 works and counts the sequences of 2N = 28 = 256 clock pulses and increments the contents of counter 2 so that the latter counts a number of pulses that it sends to it at each sequence, in order to obtain a total of 256 sequences in the interval. When the interval signal is received again (here the VFback signal), the state of counter 2 is recorded in register 9 by applying the interval signal to the transfer inputs of register 3. Bit 0 is recorded in the same way.

This concludes the interval measurement phase. It can be seen that this measurement phase is particularly interesting when, while watching a television program broadcast according to a given standard, a user switches to a program broadcast according to a different standard: a different way in which the images are shown more or less finely. In each case, the time used to learn the characteristics of the image is one frame interval. This is not critical and will definitely be accepted by the user if he wishes to make a program change - especially with his remote control.

Once the state of counter 2 has been detected, the counters are reset and the connections of the counters are reorganized so that the diagram changes to that shown in Figure 4. In practice, we are dealing with a microprocessor system, as we will see below, and so the reorganization is quite simple. The counter/downcounter 2 is then initialized by writing the contents of register 3 into it. The downcounting is then started. As soon as a count of P clock pulses is reached, the state of counter 5 is changed. This change of state results in a new value being read from memory 6 and loaded into register 15. Register 15 is read at the frequency of the HSYNC signal, i.e. the frequency of the deflection of the lines. This phenomenon repeats itself as long as no new signal is received at the end of the interval.

When a signal is received from the end of the interval, we return to initialization. This means that at that moment we start again to load counter 2 with the contents of register 3, and so on. We can nevertheless proceed in two ways. Either we count 2N different changes of state to start a new cycle with 2N states. Or we rely more on the end of the interval signal VFback to perform a new synchronization. In all cases, we reinitialize counter 2 with the contents of register 3 at the beginning of the interval.

Figure 4 shows a representation of an embodiment of the invention with a microprocessor circuit and with a bus. In this representation, the two counters 5 and 2 are implemented in a single counter with N+M bits = 17 bits as an example. This counter receives the commands through a processor 23 which also controls the command and data register 3. The counter receives the clock signals at 4 MHz and the raster signal VFback: the interval signal. The circuit also comprises a data bus 24, an address bus 25 and an input/output multiplexer 26. The input/output multiplexer makes it possible to store in the memory 6 of a circuit associated with the monitor 8 measured correction coefficients for the monitor and stored in advance in a memory 27 connected to the bus 24 and 25. The multiplexer 26 also allows the memory 6 to be managed by the microprocessor 6. The reorganization of the connection of the counters is carried out by the microprocessor 23 according to the following principle. Each connection of the elements in figures 1 and 2 is made with the other elements by a circuit comprising an AND gate. This AND gate receives the signal to be transmitted as well as an active or inactive control signal. It only transmits the signal to be transmitted in the first case. With the control signal active during the measurement phase and the control signal inactive during the use phase, it is easy to make a change. For example, with each program change, the control signal will only be active for the duration of the first grid. In other applications, one can also imagine a control input in order to be able to apply this control signal at will.

Claims (8)

1. Deflection signal generating circuit for display screens with a generator of periodic signals of a predetermined shape, comprising: - a clock generator (1) for outputting a number A pulses during a selected duration for the periodic signals, where A is less than or equal to 2N+M, where N and M are integers, - a first numerical binary counter (2) for counting a sequence of P pulses from the clock generator with M-bit counting width, where 2M is greater than or equal to P, which receives the clock generator pulses via its counting input, wherein the P pulses from the clock generator occur during 1/(2N) fractions of said selected duration, and which outputs a sequence signal at each counting sequence, - a second numerical binary counter (5) with N-bit cycle, which reads the said sequence signal via its counting input and outputs an address signal each time a sequence signal is counted, - a memory (6) with at least 2N addresses that can be accessed at will, which is provided with an address input and a data output, which is connected via its address input to the output of the second counter and outputs via its output binary signals that correspond to the generated address signals, and - a converter circuit (13) connected to the output of the memory for generating said periodic signal as a function of the received binary signals, characterized in that the generating circuit comprises a circuit for recording the value P on the basis of the counting of the number A during a selected period, and in that - the first counter (2) is programmable via the generator circuit to the value P thus recorded. 2. Circuit according to claim 1, characterized in that the converter circuit (13) comprises at the input a transfer register (15) which is connected via its input to the output of the random access memory and is equipped with a transfer control input (HSYNC). 3. Circuit according to one of claims 1 or 2, characterized in that the second counter (5) comprises an input for resetting to zero, which is triggered by a signal (VFback) after the selected duration. 4. Circuit according to one of claims 1 to 3, characterized in that it comprises a setting register (3) for setting the first counter into a predetermined state when starting the counting of the pulse sequence and a comparator circuit (4) for comparing the counter state with a predetermined state at any time. 5. Circuit according to claim 4, characterized in that the first counter (2) is a down counter, and in that the comparator circuit comprises an OR or NOR gate (4) with M inputs. 6. Circuit according to one of claims 4 or 5, characterized in that it comprises a logic circuit (23) for connecting the first and second counters and the setting register differently in another connection mode. 7. Circuit according to claim 6, characterized in that in the other connection mode - the second numerical binary counter (5) receives the signal from the clock generator (1) via its counting input with an N-bit cycle, - the first numerical binary counter (2) with M-bit receives the counting pulses coming from the last stage of the second counter (5) via its counting input, - the two counters are connected to the setting register (3) to receive and load a setting signal corresponding to the content P of the first counter (2) and a part of the second counter, the setting register comprising an input for control triggered by a signal (VFback) after a selected duration. 8. Circuit according to one of claims 1 to 7, characterized in that the second counter (5) comprises an input for resetting to zero by means of a signal for synchronizing the field (VFback) of the television screen.