DE69329897T2 - Verfahren zur Verbesserung der Eigenschaften der Grenzfläche CaF2 auf Silizium - Google Patents

Verfahren zur Verbesserung der Eigenschaften der Grenzfläche CaF2 auf Silizium

Info

Publication number
DE69329897T2
DE69329897T2 DE69329897T DE69329897T DE69329897T2 DE 69329897 T2 DE69329897 T2 DE 69329897T2 DE 69329897 T DE69329897 T DE 69329897T DE 69329897 T DE69329897 T DE 69329897T DE 69329897 T2 DE69329897 T2 DE 69329897T2
Authority
DE
Germany
Prior art keywords
caf2
silicon
improving
properties
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69329897T
Other languages
English (en)
Other versions
DE69329897D1 (de
Inventor
Chih-Chen Cho
Bruce E Gnade
Hung-Yu Liu
Tae Seung Kim
Yasushiro Nishioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69329897D1 publication Critical patent/DE69329897D1/de
Application granted granted Critical
Publication of DE69329897T2 publication Critical patent/DE69329897T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02301—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment in-situ cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02269—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by thermal evaporation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/91—Controlling charging state at semiconductor-insulator interface

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Formation Of Insulating Films (AREA)
  • Physical Vapour Deposition (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
DE69329897T 1992-02-28 1993-02-18 Verfahren zur Verbesserung der Eigenschaften der Grenzfläche CaF2 auf Silizium Expired - Fee Related DE69329897T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/843,038 US5229333A (en) 1992-02-28 1992-02-28 Method for improving the interface characteristics of CaF2 on silicon

Publications (2)

Publication Number Publication Date
DE69329897D1 DE69329897D1 (de) 2001-03-08
DE69329897T2 true DE69329897T2 (de) 2001-07-19

Family

ID=25288913

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69329897T Expired - Fee Related DE69329897T2 (de) 1992-02-28 1993-02-18 Verfahren zur Verbesserung der Eigenschaften der Grenzfläche CaF2 auf Silizium

Country Status (4)

Country Link
US (1) US5229333A (de)
EP (1) EP0562273B1 (de)
JP (1) JPH06256949A (de)
DE (1) DE69329897T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5529640A (en) * 1993-06-21 1996-06-25 Texas Instruments Incorporated Epitaxial metal-insulator-metal-semiconductor structures
US5494850A (en) * 1994-03-01 1996-02-27 Texas Instruments Incorporated Annealing process to improve optical properties of thin film light emitter
JPH08213640A (ja) 1994-08-15 1996-08-20 Texas Instr Inc <Ti> 窒化ｉｉｉ−ｖ化合物共鳴トンネリングダイオード
JPH08107068A (ja) * 1994-10-03 1996-04-23 Nec Corp ＭＢＥ法によるＳｉ基板上ＣｄＴｅ成長方法
US5563428A (en) * 1995-01-30 1996-10-08 Ek; Bruce A. Layered structure of a substrate, a dielectric layer and a single crystal layer
US6083849A (en) * 1995-11-13 2000-07-04 Micron Technology, Inc. Methods of forming hemispherical grain polysilicon
US6534348B1 (en) 1998-04-14 2003-03-18 Texas Instruments Incorporated Ultrascaled MIS transistors fabricated using silicon-on-lattice-matched insulator approach
US20020142478A1 (en) * 2001-03-28 2002-10-03 Hiroyuki Wado Gas sensor and method of fabricating a gas sensor

Also Published As

Publication number Publication date
JPH06256949A (ja) 1994-09-13
EP0562273A2 (de) 1993-09-29
EP0562273A3 (en) 1993-11-10
US5229333A (en) 1993-07-20
DE69329897D1 (de) 2001-03-08
EP0562273B1 (de) 2001-01-31

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee