DE69321124T2 - Verfahren zur simulation einer elektronischen schaltung mit verbesserter genauigkeit. - Google Patents
Verfahren zur simulation einer elektronischen schaltung mit verbesserter genauigkeit.Info
- Publication number
- DE69321124T2 DE69321124T2 DE69321124T DE69321124T DE69321124T2 DE 69321124 T2 DE69321124 T2 DE 69321124T2 DE 69321124 T DE69321124 T DE 69321124T DE 69321124 T DE69321124 T DE 69321124T DE 69321124 T2 DE69321124 T2 DE 69321124T2
- Authority
- DE
- Germany
- Prior art keywords
- simulation model
- evaluation
- levelization
- model
- asynchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/920,118 US5392227A (en) | 1992-07-24 | 1992-07-24 | System and method for generating electronic circuit simulation models having improved accuracy |
PCT/US1993/005155 WO1994002906A1 (en) | 1992-07-24 | 1993-06-01 | System and method for generating electronic circuit simulation models having improved accuracy |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69321124D1 DE69321124D1 (de) | 1998-10-22 |
DE69321124T2 true DE69321124T2 (de) | 1999-05-06 |
Family
ID=25443198
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69321124T Expired - Fee Related DE69321124T2 (de) | 1992-07-24 | 1993-06-01 | Verfahren zur simulation einer elektronischen schaltung mit verbesserter genauigkeit. |
Country Status (6)
Country | Link |
---|---|
US (1) | US5392227A (de) |
EP (1) | EP0651901B1 (de) |
JP (1) | JPH08503794A (de) |
AT (1) | ATE171288T1 (de) |
DE (1) | DE69321124T2 (de) |
WO (1) | WO1994002906A1 (de) |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5530841A (en) * | 1990-12-21 | 1996-06-25 | Synopsys, Inc. | Method for converting a hardware independent user description of a logic circuit into hardware components |
JP3082987B2 (ja) * | 1991-10-09 | 2000-09-04 | 株式会社日立製作所 | ミックスモードシミュレーション方法 |
US5559715A (en) * | 1992-03-11 | 1996-09-24 | Vlsi Technology, Inc. | Timing model and characterization system for logic simulation of integrated circuits which takes into account process, temperature and power supply variations |
JP3099310B2 (ja) * | 1993-03-15 | 2000-10-16 | 株式会社東芝 | 回路解析装置 |
US5812431A (en) * | 1994-06-13 | 1998-09-22 | Cadence Design Systems, Inc. | Method and apparatus for a simplified system simulation description |
US5581489A (en) * | 1994-01-05 | 1996-12-03 | Texas Instruments Incorporated | Model generator for constructing and method of generating a model of an object for finite element analysis |
US5650947A (en) * | 1994-01-31 | 1997-07-22 | Fujitsu Limited | Logic simulation method and logic simulator |
GB9406931D0 (en) * | 1994-04-07 | 1994-06-01 | Philips Electronics Uk Ltd | Data processing apparatus |
US5673420A (en) * | 1994-06-06 | 1997-09-30 | Motorola, Inc. | Method of generating power vectors for cell power dissipation simulation |
GB9413127D0 (en) * | 1994-06-30 | 1994-08-24 | Philips Electronics Uk Ltd | Data processing apparatus |
US5752000A (en) * | 1994-08-02 | 1998-05-12 | Cadence Design Systems, Inc. | System and method for simulating discrete functions using ordered decision arrays |
US5539680A (en) * | 1994-08-03 | 1996-07-23 | Sun Microsystem, Inc. | Method and apparatus for analyzing finite state machines |
US5638291A (en) * | 1994-10-14 | 1997-06-10 | Vlsi Technology, Inc. | Method and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skew |
US6053948A (en) * | 1995-06-07 | 2000-04-25 | Synopsys, Inc. | Method and apparatus using a memory model |
US5953519A (en) * | 1995-06-12 | 1999-09-14 | Fura; David A. | Method and system for generating electronic hardware simulation models |
US5809283A (en) * | 1995-09-29 | 1998-09-15 | Synopsys, Inc. | Simulator for simulating systems including mixed triggers |
US6212668B1 (en) | 1996-05-28 | 2001-04-03 | Altera Corporation | Gain matrix for hierarchical circuit partitioning |
US5867395A (en) * | 1996-06-19 | 1999-02-02 | Lsi Logic Corporation | Gate netlist to register transfer level conversion tool |
US5857093A (en) * | 1996-09-20 | 1999-01-05 | Allen-Bradley Company, Llc | Cross-compiled simulation timing backannotation |
US6301694B1 (en) | 1996-09-25 | 2001-10-09 | Altera Corporation | Hierarchical circuit partitioning using sliding windows |
US6023567A (en) * | 1996-10-07 | 2000-02-08 | International Business Machines Corporation | Method and apparatus for verifying timing rules for an integrated circuit design |
US6304836B1 (en) * | 1996-10-28 | 2001-10-16 | Advanced Micro Devices | Worst case design parameter extraction for logic technologies |
US5987238A (en) * | 1996-11-29 | 1999-11-16 | Cadence Design Systems, Inc. | Method and system for simulating and making a phase lock loop circuit |
US6028993A (en) * | 1997-01-10 | 2000-02-22 | Lucent Technologies Inc. | Timed circuit simulation in hardware using FPGAs |
US6049662A (en) * | 1997-01-27 | 2000-04-11 | International Business Machines Corporation | System and method for model size reduction of an integrated circuit utilizing net invariants |
FR2759826B1 (fr) * | 1997-02-14 | 1999-12-17 | Sgs Thomson Microelectronics | Procede de simulation precise de circuits logiques |
US6099579A (en) * | 1997-10-02 | 2000-08-08 | Hewlett-Packard Company | Method and apparatus for checking asynchronous HDL circuit designs |
US6311146B1 (en) * | 1997-12-05 | 2001-10-30 | Lucent Technologies Inc. | Circuit simulation with improved circuit partitioning |
US6295517B1 (en) * | 1998-04-07 | 2001-09-25 | Synopsis, Inc. | Method and apparatus for adaptively or selectively choosing event-triggered cycle-based simulation or oblivious-triggered cycle-based simulation on a cluster-by-cluster basis |
JP2001216346A (ja) | 2000-02-04 | 2001-08-10 | Mitsubishi Electric Corp | 論理シミュレーション方法および論理シミュレーション装置 |
WO2002101597A1 (fr) * | 2001-06-12 | 2002-12-19 | Tops Systems Corporation | Procede de planification pour simuler un circuit sequentiel par procede sur base cyclique |
US6701498B2 (en) | 2001-11-08 | 2004-03-02 | Sun Microsystems, Inc. | Black box timing model for latch-based systems |
US6611949B2 (en) * | 2001-11-08 | 2003-08-26 | Sun Microsystems, Inc. | Path filtering for latch-based systems |
US6657500B1 (en) | 2002-01-08 | 2003-12-02 | Taiwan Semiconductor Manufacturing Company | Method and system of characterization and behavioral modeling of a phase-locked loop for fast mixed signal simulation |
US7039887B2 (en) * | 2002-10-15 | 2006-05-02 | Cadence Design Systems, Inc. | Method and apparatus for enhancing the performance of event driven dynamic simulation of digital circuits based on netlist partitioning techniques |
US7283942B1 (en) * | 2002-11-26 | 2007-10-16 | Altera Corporation | High speed techniques for simulating circuits |
US20050197807A1 (en) * | 2004-03-04 | 2005-09-08 | Jerimy Nelson | System and method for maintaining homogeneity between a model in a computer-aided modeling system and corresponding model documentation |
US20060203581A1 (en) * | 2005-03-10 | 2006-09-14 | Joshi Rajiv V | Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions |
US20070098020A1 (en) * | 2005-10-27 | 2007-05-03 | Yee Ja | Methods and arrangements to model an asynchronous interface |
US7424691B2 (en) * | 2006-04-11 | 2008-09-09 | International Business Machines Corporation | Method for verifying performance of an array by simulating operation of edge cells in a full array model |
US8594988B1 (en) | 2006-07-18 | 2013-11-26 | Cadence Design Systems, Inc. | Method and apparatus for circuit simulation using parallel computing |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55153054A (en) * | 1979-05-15 | 1980-11-28 | Hitachi Ltd | Logic circuit simulation system |
US5067091A (en) * | 1988-01-21 | 1991-11-19 | Kabushiki Kaisha Toshiba | Circuit design conversion apparatus |
WO1990004233A1 (en) * | 1988-10-05 | 1990-04-19 | Mentor Graphics Corporation | Method of using electronically reconfigurable gate array logic and apparatus formed thereby |
US5062067A (en) * | 1989-03-15 | 1991-10-29 | Vlsi Technology, Inc. | Levelized logic simulator with fenced evaluation |
US5068812A (en) * | 1989-07-18 | 1991-11-26 | Vlsi Technology, Inc. | Event-controlled LCC stimulation |
-
1992
- 1992-07-24 US US07/920,118 patent/US5392227A/en not_active Expired - Lifetime
-
1993
- 1993-06-01 EP EP93915169A patent/EP0651901B1/de not_active Expired - Lifetime
- 1993-06-01 AT AT93915169T patent/ATE171288T1/de active
- 1993-06-01 JP JP6504435A patent/JPH08503794A/ja active Pending
- 1993-06-01 WO PCT/US1993/005155 patent/WO1994002906A1/en active IP Right Grant
- 1993-06-01 DE DE69321124T patent/DE69321124T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0651901A1 (de) | 1995-05-10 |
EP0651901B1 (de) | 1998-09-16 |
WO1994002906A1 (en) | 1994-02-03 |
ATE171288T1 (de) | 1998-10-15 |
US5392227A (en) | 1995-02-21 |
DE69321124D1 (de) | 1998-10-22 |
JPH08503794A (ja) | 1996-04-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |