DE69314360D1 - Nichtinvertierendes logisches Tor - Google Patents

Nichtinvertierendes logisches Tor

Info

Publication number
DE69314360D1
DE69314360D1 DE69314360T DE69314360T DE69314360D1 DE 69314360 D1 DE69314360 D1 DE 69314360D1 DE 69314360 T DE69314360 T DE 69314360T DE 69314360 T DE69314360 T DE 69314360T DE 69314360 D1 DE69314360 D1 DE 69314360D1
Authority
DE
Germany
Prior art keywords
logic gate
inverting logic
inverting
gate
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69314360T
Other languages
English (en)
Other versions
DE69314360T2 (de
Inventor
Cong Khieu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Semiconductor Inc
Original Assignee
Samsung Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/824,630 external-priority patent/US5243237A/en
Application filed by Samsung Semiconductor Inc filed Critical Samsung Semiconductor Inc
Application granted granted Critical
Publication of DE69314360D1 publication Critical patent/DE69314360D1/de
Publication of DE69314360T2 publication Critical patent/DE69314360T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
DE1993614360 1992-01-22 1993-01-21 Nichtinvertierendes logisches Tor Expired - Lifetime DE69314360T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/824,630 US5243237A (en) 1992-01-22 1992-01-22 Noninverting bi-cmos gates with propagation delays of a single bi-cmos inverter

Publications (2)

Publication Number Publication Date
DE69314360D1 true DE69314360D1 (de) 1997-11-13
DE69314360T2 DE69314360T2 (de) 1998-01-29

Family

ID=25241902

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1993614360 Expired - Lifetime DE69314360T2 (de) 1992-01-22 1993-01-21 Nichtinvertierendes logisches Tor

Country Status (3)

Country Link
EP (1) EP0552963B1 (de)
DE (1) DE69314360T2 (de)
TW (1) TW311301B (de)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2865256B2 (ja) * 1989-03-02 1999-03-08 株式会社日立製作所 バイポーラ・ｍｏｓ論理回路
JP2570492B2 (ja) * 1990-11-28 1997-01-08 日本電気株式会社 半導体回路

Also Published As

Publication number Publication date
TW311301B (de) 1997-07-21
DE69314360T2 (de) 1998-01-29
EP0552963A3 (en) 1993-12-08
EP0552963A2 (de) 1993-07-28
EP0552963B1 (de) 1997-10-08

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