DE69308407D1 - Verfahren zur automatischen Erzeugung von Prüfsequenzen - Google Patents

Verfahren zur automatischen Erzeugung von Prüfsequenzen

Info

Publication number
DE69308407D1
DE69308407D1 DE69308407T DE69308407T DE69308407D1 DE 69308407 D1 DE69308407 D1 DE 69308407D1 DE 69308407 T DE69308407 T DE 69308407T DE 69308407 T DE69308407 T DE 69308407T DE 69308407 D1 DE69308407 D1 DE 69308407D1
Authority
DE
Germany
Prior art keywords
test sequences
automatic generation
procedure
sequences
impossibilities
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69308407T
Other languages
English (en)
Other versions
DE69308407T2 (de
Inventor
De Burgt Stephanus Pieter Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke PTT Nederland NV
Original Assignee
Koninklijke PTT Nederland NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke PTT Nederland NV filed Critical Koninklijke PTT Nederland NV
Application granted granted Critical
Publication of DE69308407D1 publication Critical patent/DE69308407D1/de
Publication of DE69308407T2 publication Critical patent/DE69308407T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Investigating, Analyzing Materials By Fluorescence Or Luminescence (AREA)
  • Computer And Data Communications (AREA)
  • Debugging And Monitoring (AREA)
  • Medicinal Preparation (AREA)
  • Communication Control (AREA)
  • Investigating Or Analysing Biological Materials (AREA)
  • Facsimiles In General (AREA)
DE69308407T 1992-07-02 1993-06-18 Verfahren zur automatischen Erzeugung von Prüfsequenzen Expired - Fee Related DE69308407T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL9201182A NL9201182A (nl) 1992-07-02 1992-07-02 Methode voor het automatisch genereren van testreeksen.

Publications (2)

Publication Number Publication Date
DE69308407D1 true DE69308407D1 (de) 1997-04-10
DE69308407T2 DE69308407T2 (de) 1997-08-07

Family

ID=19861005

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69308407T Expired - Fee Related DE69308407T2 (de) 1992-07-02 1993-06-18 Verfahren zur automatischen Erzeugung von Prüfsequenzen

Country Status (6)

Country Link
US (1) US5426651A (de)
EP (1) EP0579302B1 (de)
AT (1) ATE149708T1 (de)
DE (1) DE69308407T2 (de)
ES (1) ES2100442T3 (de)
NL (1) NL9201182A (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6282681B1 (en) * 1995-03-06 2001-08-28 Motorola, Inc. Method and apparatus for testing finite state machine (FSM) conformance utilizing unique input/output sequence (UIO) sets
US6004027A (en) * 1995-03-06 1999-12-21 Motorola Inc. Method and apparatus for constructing test subsequence graphs utilizing unique input/output sequence (UIO) sets
US5796752A (en) * 1995-03-06 1998-08-18 Motorola, Inc. Method and apparatus for constructing verification test sequences by euler touring a test subsequence graph
US5630051A (en) * 1995-03-06 1997-05-13 Motorola Inc. Method and apparatus for merging hierarchical test subsequence and finite state machine (FSM) model graphs
US5703885A (en) * 1995-03-06 1997-12-30 Motorola, Inc. Method and apparatus for constructing verification test sequences by merging and touring hierarchical unique input/output sequence (UIO) based test subsequence graphs
US5555270A (en) * 1995-03-13 1996-09-10 Motorola Inc. Method and apparatus for constructing unique input/output sequence (UIO) sets utilizing transition distinctness measurements
US5787147A (en) * 1995-12-21 1998-07-28 Ericsson Inc. Test message generator in a telecommunications network
US6487676B1 (en) 1996-07-19 2002-11-26 Telefonaktiebolaget Lm Ericsson (Publ) Validation of procedures
GB2315646B (en) * 1996-07-19 2001-02-14 Ericsson Telefon Ab L M Validation of procedures
US5933633A (en) * 1996-11-19 1999-08-03 Good; Sebastian Erich State table generating system
US5987251A (en) * 1997-09-03 1999-11-16 Mci Communications Corporation Automated document checking tool for checking sufficiency of documentation of program instructions
US6321376B1 (en) * 1997-10-27 2001-11-20 Ftl Systems, Inc. Apparatus and method for semi-automated generation and application of language conformity tests
US6553514B1 (en) * 1999-09-23 2003-04-22 International Business Machines Corporation Digital circuit verification
DE10127690A1 (de) * 2001-06-08 2002-12-12 Infineon Technologies Ag Verfahren zur Erzeugung von Testmustern zur Prüfung von elektrischen Schaltungen
US20050194166A1 (en) * 2003-06-10 2005-09-08 Goodti Industrial Co., Ltd. High torque electromotive tool
US7882473B2 (en) 2007-11-27 2011-02-01 International Business Machines Corporation Sequential equivalence checking for asynchronous verification

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4764863A (en) * 1985-05-09 1988-08-16 The United States Of America As Represented By The Secretary Of Commerce Hardware interpreter for finite state automata
US4692921A (en) * 1985-08-22 1987-09-08 American Telephone And Telegraph Company, At&T Bell Laboratories Method for generating verification tests
GB8527913D0 (en) * 1985-11-12 1985-12-18 Pa Consulting Services Analysing transitions in finite state machines
US4991176A (en) * 1989-06-07 1991-02-05 At&T Bell Laboratories Optimal test generation for finite state machine models
DE69126199T2 (de) * 1991-02-21 1997-10-16 Ibm Integrierter Schaltkreis mit eingebautem Selbsttest für die Erkennung logischer Fehler

Also Published As

Publication number Publication date
ATE149708T1 (de) 1997-03-15
DE69308407T2 (de) 1997-08-07
US5426651A (en) 1995-06-20
ES2100442T3 (es) 1997-06-16
EP0579302A1 (de) 1994-01-19
EP0579302B1 (de) 1997-03-05
NL9201182A (nl) 1994-02-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee