DE69231520D1 - Ausgang einer logischen makrozelle mit verbesserten funktionsmöglichkeiten - Google Patents

Ausgang einer logischen makrozelle mit verbesserten funktionsmöglichkeiten

Info

Publication number
DE69231520D1
DE69231520D1 DE69231520T DE69231520T DE69231520D1 DE 69231520 D1 DE69231520 D1 DE 69231520D1 DE 69231520 T DE69231520 T DE 69231520T DE 69231520 T DE69231520 T DE 69231520T DE 69231520 D1 DE69231520 D1 DE 69231520D1
Authority
DE
Germany
Prior art keywords
output
improved functionality
macrocell
logical
logical macrocell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69231520T
Other languages
English (en)
Other versions
DE69231520T2 (de
Inventor
Ju Shen
L Chan
Kapil Shankar
Cyrus Tsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lattice Semiconductor Corp
Original Assignee
Lattice Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lattice Semiconductor Corp filed Critical Lattice Semiconductor Corp
Publication of DE69231520D1 publication Critical patent/DE69231520D1/de
Application granted granted Critical
Publication of DE69231520T2 publication Critical patent/DE69231520T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
DE69231520T 1991-05-06 1992-04-29 Ausgang einer logischen makrozelle mit verbesserten funktionsmöglichkeiten Expired - Fee Related DE69231520T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/696,907 US5191243A (en) 1991-05-06 1991-05-06 Output logic macrocell with enhanced functional capabilities
PCT/US1992/003618 WO1992020155A1 (en) 1991-05-06 1992-04-29 Output logic macrocell with enhanced functional capabilities

Publications (2)

Publication Number Publication Date
DE69231520D1 true DE69231520D1 (de) 2000-11-23
DE69231520T2 DE69231520T2 (de) 2001-05-17

Family

ID=24799021

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69231520T Expired - Fee Related DE69231520T2 (de) 1991-05-06 1992-04-29 Ausgang einer logischen makrozelle mit verbesserten funktionsmöglichkeiten

Country Status (5)

Country Link
US (1) US5191243A (de)
EP (1) EP0583371B1 (de)
JP (1) JP3519402B2 (de)
DE (1) DE69231520T2 (de)
WO (1) WO1992020155A1 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5457409A (en) * 1992-08-03 1995-10-10 Advanced Micro Devices, Inc. Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices
US5489857A (en) * 1992-08-03 1996-02-06 Advanced Micro Devices, Inc. Flexible synchronous/asynchronous cell structure for a high density programmable logic device
US5861760A (en) * 1991-04-25 1999-01-19 Altera Corporation Programmable logic device macrocell with improved capability
US20020130681A1 (en) * 1991-09-03 2002-09-19 Cliff Richard G. Programmable logic array integrated circuits
US6759870B2 (en) 1991-09-03 2004-07-06 Altera Corporation Programmable logic array integrated circuits
US5386154A (en) * 1992-07-23 1995-01-31 Xilinx, Inc. Compact logic cell for field programmable gate array chip
US5646547A (en) * 1994-04-28 1997-07-08 Xilinx, Inc. Logic cell which can be configured as a latch without static one's problem
US5365125A (en) * 1992-07-23 1994-11-15 Xilinx, Inc. Logic cell for field programmable gate array having optional internal feedback and optional cascade
DE69304471T2 (de) * 1992-08-03 1997-03-20 Advanced Micro Devices Inc Programmierbare logische Vorrichtung
US5399922A (en) * 1993-07-02 1995-03-21 Altera Corporation Macrocell comprised of two look-up tables and two flip-flops
US5404055A (en) * 1993-09-01 1995-04-04 Lattice Semiconductor Corporation Input routing pool
US5581200A (en) * 1994-03-04 1996-12-03 Gudger; Keith H. Stored and combinational logic function generator without dedicated storage elements
US5521529A (en) * 1995-06-02 1996-05-28 Advanced Micro Devices, Inc. Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation
US5818254A (en) * 1995-06-02 1998-10-06 Advanced Micro Devices, Inc. Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices
US6028446A (en) * 1995-06-06 2000-02-22 Advanced Micro Devices, Inc. Flexible synchronous and asynchronous circuits for a very high density programmable logic device
US5629635A (en) * 1995-09-26 1997-05-13 Ics Technologies, Inc. Address programming via LED pin
US5670896A (en) * 1995-09-26 1997-09-23 Xilinx, Inc. High speed product term assignment for output enable, clock, inversion and set/reset in a programmable logic device
US5635856A (en) * 1995-10-03 1997-06-03 Cypress Semiconductor Corporation High speed programmable macrocell with combined path for storage and combinatorial modes
USRE37577E1 (en) 1996-01-11 2002-03-12 Cypress Semiconductor Corporation High speed configuration independent programmable macrocell
US5832250A (en) * 1996-01-26 1998-11-03 Unisys Corporation Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bits
US5966029A (en) * 1997-07-15 1999-10-12 Motorola, Inc. Multi-bit exclusive or
US6191612B1 (en) * 1998-11-19 2001-02-20 Vantis Corporation Enhanced I/O control flexibility for generating control signals
US6720796B1 (en) 2001-05-06 2004-04-13 Altera Corporation Multiple size memories in a programmable logic device
US6747480B1 (en) 2002-07-12 2004-06-08 Altera Corporation Programmable logic devices with bidirect ional cascades
US7613853B2 (en) * 2003-10-24 2009-11-03 Stmicroelectronics Pvt. Ltd. Output buffer circuit capable of synchronous and asynchronous data buffering using sensing circuit, and method and system of same
US7231582B2 (en) * 2003-12-19 2007-06-12 Stmicroelectronics, Inc. Method and system to encode and decode wide data words
JP4706042B2 (ja) * 2005-11-07 2011-06-22 ルネサスエレクトロニクス株式会社 マクロセル回路
JP5228803B2 (ja) * 2008-10-30 2013-07-03 富士通セミコンダクター株式会社 共通鍵ブロック暗号におけるスワップ回路及び、それを有する暗号化・復号化回路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4896296A (en) * 1985-03-04 1990-01-23 Lattice Semiconductor Corporation Programmable logic device configurable input/output cell
US4758746A (en) * 1985-08-12 1988-07-19 Monolithic Memories, Inc. Programmable logic array with added array of gates and added output routing flexibility
US4789951A (en) * 1986-05-16 1988-12-06 Advanced Micro Devices, Inc. Programmable array logic cell
US4918641A (en) * 1987-08-26 1990-04-17 Ict International Cmos Technology, Inc. High-performance programmable logic device
US4912342A (en) * 1988-05-05 1990-03-27 Altera Corporation Programmable logic device with array blocks with programmable clocking
US4879481A (en) * 1988-09-02 1989-11-07 Cypress Semiconductor Corporation Dual I/O macrocell for high speed synchronous state machine
US4912345A (en) * 1988-12-29 1990-03-27 Sgs-Thomson Microelectronics, Inc. Programmable summing functions for programmable logic devices

Also Published As

Publication number Publication date
EP0583371B1 (de) 2000-10-18
WO1992020155A1 (en) 1992-11-12
DE69231520T2 (de) 2001-05-17
JPH06507054A (ja) 1994-08-04
EP0583371A4 (de) 1993-11-16
EP0583371A1 (de) 1994-02-23
JP3519402B2 (ja) 2004-04-12
US5191243A (en) 1993-03-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee