DE69229531D1 - Data security devices for programmable logic semiconductor circuits - Google Patents

Data security devices for programmable logic semiconductor circuits

Info

Publication number
DE69229531D1
DE69229531D1 DE69229531T DE69229531T DE69229531D1 DE 69229531 D1 DE69229531 D1 DE 69229531D1 DE 69229531 T DE69229531 T DE 69229531T DE 69229531 T DE69229531 T DE 69229531T DE 69229531 D1 DE69229531 D1 DE 69229531D1
Authority
DE
Germany
Prior art keywords
configuration data
pld
data
read
decoding means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69229531T
Other languages
German (de)
Other versions
DE69229531T2 (en
Inventor
Kenneth Austin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69229531D1 publication Critical patent/DE69229531D1/en
Publication of DE69229531T2 publication Critical patent/DE69229531T2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Storage Device Security (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A data security arrangement is provided to protect configuration data to be stored in static random access memories (38) in semiconductor programmable logic devices PLD. The configuration data, which is vulnerable to illegal duplication, is normally held in a read only memory ROM, typically an erasable programmable read only memory. A data coding means is provided to code the configuration data to be loaded to the PLD and a data decoding means is provided in the PLD to decode the coded configuration data. The coding and decoding means each incorporate maximal length shift registers (12, 25) which generate a pseudo-random sequence of bits. A key value is input to the shift register (12) in the coding means forcing it to start at a particular point in the sequence. The output (bits B28 and B31) of this register is combined in an EXCLUSIVE-OR gate (20) with configuration data and coded data is written to the read only memory ROM (24). The decoding means in the PLD has a corresponding key value held in a non-volatile memory (28) in the PLD. This is applied to the register (25) of the decoding means whose output (bits B28 and B31) are combined in an EXCLUSIVE-OR GATE (34) with coded configuration data CDIC read from the ROM (24) to produce decoded configuration data CDOD to be sotred in the memories (38). <IMAGE>
DE69229531T 1991-10-11 1992-09-30 Data security devices for programmable logic semiconductor circuits Expired - Fee Related DE69229531T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB919121591A GB9121591D0 (en) 1991-10-11 1991-10-11 Data security arrangement for semiconductor programmable logic devices

Publications (2)

Publication Number Publication Date
DE69229531D1 true DE69229531D1 (en) 1999-08-12
DE69229531T2 DE69229531T2 (en) 2000-03-23

Family

ID=10702763

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69229531T Expired - Fee Related DE69229531T2 (en) 1991-10-11 1992-09-30 Data security devices for programmable logic semiconductor circuits

Country Status (8)

Country Link
US (1) US5388157A (en)
EP (1) EP0536943B1 (en)
JP (1) JP3324001B2 (en)
KR (1) KR100301265B1 (en)
AT (1) ATE182016T1 (en)
CA (1) CA2080299C (en)
DE (1) DE69229531T2 (en)
GB (1) GB9121591D0 (en)

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US5768372A (en) * 1996-03-13 1998-06-16 Altera Corporation Method and apparatus for securing programming data of a programmable logic device
JP3783800B2 (en) * 1996-08-09 2006-06-07 富士通株式会社 Encryption / decryption device and method using programmable logic device / device
US5970142A (en) * 1996-08-26 1999-10-19 Xilinx, Inc. Configuration stream encryption
US6356637B1 (en) 1998-09-18 2002-03-12 Sun Microsystems, Inc. Field programmable gate arrays
US6654889B1 (en) * 1999-02-19 2003-11-25 Xilinx, Inc. Method and apparatus for protecting proprietary configuration data for programmable logic devices
US20070288765A1 (en) * 1999-12-22 2007-12-13 Kean Thomas A Method and Apparatus for Secure Configuration of a Field Programmable Gate Array
GB9930145D0 (en) 1999-12-22 2000-02-09 Kean Thomas A Method and apparatus for secure configuration of a field programmable gate array
US7240218B2 (en) * 2000-02-08 2007-07-03 Algotronix, Ltd. Method of using a mask programmed key to securely configure a field programmable gate array
ATE406698T1 (en) * 2000-07-04 2008-09-15 Sun Microsystems Inc USER PROGRAMMABLE GATES (FPGA) AND METHOD FOR EDITING FPGA CONFIGURATION DATA
US6331784B1 (en) 2000-07-28 2001-12-18 Atmel Corporation Secure programmable logic device
US7484081B1 (en) 2000-10-10 2009-01-27 Altera Corporation Method and apparatus for protecting designs in SRAM-based programmable logic devices
US7058177B1 (en) 2000-11-28 2006-06-06 Xilinx, Inc. Partially encrypted bitstream method
US6366117B1 (en) 2000-11-28 2002-04-02 Xilinx, Inc. Nonvolatile/battery-backed key in PLD
US6965675B1 (en) 2000-11-28 2005-11-15 Xilinx, Inc. Structure and method for loading encryption keys through a test access port
US6981153B1 (en) 2000-11-28 2005-12-27 Xilinx, Inc. Programmable logic device with method of preventing readback
US6957340B1 (en) 2000-11-28 2005-10-18 Xilinx, Inc. Encryption key for multi-key encryption in programmable logic device
US6441641B1 (en) * 2000-11-28 2002-08-27 Xilinx, Inc. Programmable logic device with partial battery backup
US7117373B1 (en) 2000-11-28 2006-10-03 Xilinx, Inc. Bitstream for configuring a PLD with encrypted design data
US7117372B1 (en) 2000-11-28 2006-10-03 Xilinx, Inc. Programmable logic device with decryption and structure for preventing design relocation
US6931543B1 (en) 2000-11-28 2005-08-16 Xilinx, Inc. Programmable logic device with decryption algorithm and decryption key
US6941456B2 (en) * 2001-05-02 2005-09-06 Sun Microsystems, Inc. Method, system, and program for encrypting files in a computer system
GB0114317D0 (en) * 2001-06-13 2001-08-01 Kean Thomas A Method of protecting intellectual property cores on field programmable gate array
US7558967B2 (en) * 2001-09-13 2009-07-07 Actel Corporation Encryption for a stream file in an FPGA integrated circuit
JP2004007472A (en) * 2002-03-22 2004-01-08 Toshiba Corp Semiconductor integrated circuit, data transfer system, and data transfer method
US7162644B1 (en) 2002-03-29 2007-01-09 Xilinx, Inc. Methods and circuits for protecting proprietary configuration data for programmable logic devices
US6996713B1 (en) 2002-03-29 2006-02-07 Xilinx, Inc. Method and apparatus for protecting proprietary decryption keys for programmable logic devices
US7840803B2 (en) 2002-04-16 2010-11-23 Massachusetts Institute Of Technology Authentication of integrated circuits
US8051303B2 (en) * 2002-06-10 2011-11-01 Hewlett-Packard Development Company, L.P. Secure read and write access to configuration registers in computer devices
US7653820B1 (en) * 2003-10-31 2010-01-26 Xilinx, Inc. System and method for securing using decryption keys during FPGA configuration using a microcontroller
JP4294514B2 (en) * 2004-03-05 2009-07-15 シャープ株式会社 Semiconductor device and electronic device
US8566616B1 (en) 2004-09-10 2013-10-22 Altera Corporation Method and apparatus for protecting designs in SRAM-based programmable logic devices and the like
US8612772B1 (en) 2004-09-10 2013-12-17 Altera Corporation Security core using soft key
WO2006071380A2 (en) * 2004-11-12 2006-07-06 Pufco, Inc. Securely field configurable device
US7685418B1 (en) 2005-01-19 2010-03-23 Altera Corporation Mechanisms and techniques for protecting intellectual property
US8670561B1 (en) * 2005-06-02 2014-03-11 Altera Corporation Method and apparatus for limiting use of IP
JP5248328B2 (en) * 2006-01-24 2013-07-31 ヴェラヨ インク Equipment security based on signal generators
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US7906983B2 (en) * 2008-12-08 2011-03-15 Intuitive Research And Technology Programmable logic device having an embedded test logic with secure access control
US8811615B2 (en) * 2009-08-05 2014-08-19 Verayo, Inc. Index-based coding with a pseudo-random source
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Also Published As

Publication number Publication date
DE69229531T2 (en) 2000-03-23
JP3324001B2 (en) 2002-09-17
EP0536943A2 (en) 1993-04-14
KR100301265B1 (en) 2001-10-22
ATE182016T1 (en) 1999-07-15
EP0536943A3 (en) 1993-06-16
US5388157A (en) 1995-02-07
CA2080299C (en) 2002-12-24
CA2080299A1 (en) 1993-04-12
EP0536943B1 (en) 1999-07-07
GB9121591D0 (en) 1991-11-27
KR930008851A (en) 1993-05-22
JPH05257678A (en) 1993-10-08

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee