DE69229303D1 - Gemeinsame Benutzung eines Speichers zur Kommunikation zwischen Prozessoren - Google Patents

Gemeinsame Benutzung eines Speichers zur Kommunikation zwischen Prozessoren

Info

Publication number
DE69229303D1
DE69229303D1 DE69229303T DE69229303T DE69229303D1 DE 69229303 D1 DE69229303 D1 DE 69229303D1 DE 69229303 T DE69229303 T DE 69229303T DE 69229303 T DE69229303 T DE 69229303T DE 69229303 D1 DE69229303 D1 DE 69229303D1
Authority
DE
Germany
Prior art keywords
processors
communication
sharing memory
sharing
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69229303T
Other languages
English (en)
Other versions
DE69229303T2 (de
Inventor
Masaki Nasu
Hajime Sakuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69229303D1 publication Critical patent/DE69229303D1/de
Publication of DE69229303T2 publication Critical patent/DE69229303T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0692—Multiconfiguration, e.g. local and global addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Microcomputers (AREA)
  • Multi Processors (AREA)
DE69229303T 1991-07-11 1992-07-10 Gemeinsame Benutzung eines Speichers zur Kommunikation zwischen Prozessoren Expired - Fee Related DE69229303T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3170812A JPH0520278A (ja) 1991-07-11 1991-07-11 マイクロコンピユータ

Publications (2)

Publication Number Publication Date
DE69229303D1 true DE69229303D1 (de) 1999-07-08
DE69229303T2 DE69229303T2 (de) 2000-01-27

Family

ID=15911796

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69229303T Expired - Fee Related DE69229303T2 (de) 1991-07-11 1992-07-10 Gemeinsame Benutzung eines Speichers zur Kommunikation zwischen Prozessoren

Country Status (5)

Country Link
US (1) US5467461A (de)
EP (1) EP0522582B1 (de)
JP (1) JPH0520278A (de)
KR (1) KR950010529B1 (de)
DE (1) DE69229303T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2704113B2 (ja) * 1994-04-26 1998-01-26 日本電気アイシーマイコンシステム株式会社 データ処理装置
WO1996008775A1 (en) * 1994-09-16 1996-03-21 Philips Electronics N.V. Software programmable bus disable system
US5832277A (en) * 1996-03-08 1998-11-03 3 Com Corporation System for arbitrating demand on memory during configuration of a computer add-on card
GB9707364D0 (en) * 1997-04-11 1997-05-28 Eidos Technologies Limited A method and a system for processing digital information
KR100269338B1 (ko) * 1997-12-27 2000-10-16 서평원 통신시스템의사설교환기및이에구비된모듈간에데이터통신방법
US6163828A (en) * 1998-05-22 2000-12-19 Lucent Technologies Inc. Methods and apparatus for providing multi-processor access to shared memory
US6067629A (en) * 1998-08-10 2000-05-23 Intel Corporation Apparatus and method for pseudo-synchronous communication between clocks of different frequencies
US6684321B1 (en) * 2000-01-04 2004-01-27 Advanced Micro Devices, Inc. Unified memory architecture for use by a main processor and an external processor and method of operation
KR100606946B1 (ko) 2001-11-30 2006-08-01 후지쓰 텐 가부시키가이샤 마이크로 컴퓨터의 로직 개발 장치
JP2006172142A (ja) * 2004-12-16 2006-06-29 Matsushita Electric Ind Co Ltd マルチプロセッサシステム
JP4328334B2 (ja) 2006-03-13 2009-09-09 パナソニック株式会社 半導体集積回路装置
JP4267002B2 (ja) * 2006-06-08 2009-05-27 エルピーダメモリ株式会社 コントローラ及びメモリを備えるシステム
WO2008099931A1 (ja) * 2007-02-15 2008-08-21 Fujitsu Ten Limited マイクロコンピュータの模擬装置
JP2008226280A (ja) * 2008-06-25 2008-09-25 Renesas Technology Corp システムｌｓｉ

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4325116A (en) * 1979-08-21 1982-04-13 International Business Machines Corporation Parallel storage access by multiprocessors
JPS57117027A (en) * 1981-01-13 1982-07-21 Nec Corp Signal sending and receiving circuit
US4495567A (en) * 1981-10-15 1985-01-22 Codex Corporation Multiprocessor/multimemory control system
US4503497A (en) * 1982-05-27 1985-03-05 International Business Machines Corporation System for independent cache-to-cache transfer
JP2584113B2 (ja) * 1989-07-21 1997-02-19 松下電器産業株式会社 データ転送方法及びデータ転送装置

Also Published As

Publication number Publication date
JPH0520278A (ja) 1993-01-29
US5467461A (en) 1995-11-14
DE69229303T2 (de) 2000-01-27
KR930002958A (ko) 1993-02-23
KR950010529B1 (ko) 1995-09-19
EP0522582B1 (de) 1999-06-02
EP0522582A2 (de) 1993-01-13
EP0522582A3 (en) 1993-02-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee