DE69227482D1 - Überlaufdetektionssystem und dessen Schaltung zum Gebrauch beim Addieren und Substrahieren - Google Patents

Überlaufdetektionssystem und dessen Schaltung zum Gebrauch beim Addieren und Substrahieren

Info

Publication number
DE69227482D1
DE69227482D1 DE69227482T DE69227482T DE69227482D1 DE 69227482 D1 DE69227482 D1 DE 69227482D1 DE 69227482 T DE69227482 T DE 69227482T DE 69227482 T DE69227482 T DE 69227482T DE 69227482 D1 DE69227482 D1 DE 69227482D1
Authority
DE
Germany
Prior art keywords
subtracting
circuit
detection system
overflow detection
overflow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69227482T
Other languages
English (en)
Other versions
DE69227482T2 (de
Inventor
Kazumasa Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69227482D1 publication Critical patent/DE69227482D1/de
Publication of DE69227482T2 publication Critical patent/DE69227482T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Measurement Of Current Or Voltage (AREA)
DE69227482T 1991-06-28 1992-06-23 Überlaufdetektionssystem und dessen Schaltung zum Gebrauch beim Addieren und Substrahieren Expired - Fee Related DE69227482T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3185552A JP2894015B2 (ja) 1991-06-28 1991-06-28 桁あふれ検出方法および回路

Publications (2)

Publication Number Publication Date
DE69227482D1 true DE69227482D1 (de) 1998-12-10
DE69227482T2 DE69227482T2 (de) 1999-06-24

Family

ID=16172809

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69227482T Expired - Fee Related DE69227482T2 (de) 1991-06-28 1992-06-23 Überlaufdetektionssystem und dessen Schaltung zum Gebrauch beim Addieren und Substrahieren

Country Status (5)

Country Link
US (1) US5260890A (de)
EP (1) EP0520378B1 (de)
JP (1) JP2894015B2 (de)
CA (1) CA2072265C (de)
DE (1) DE69227482T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5083439A (en) * 1990-04-06 1992-01-28 Robertshaw Controls Company Control device having a shape memory wire, refrigerator system utilizing the control device and methods of making the same
JPH1091395A (ja) * 1996-09-13 1998-04-10 Toshiba Corp プロセッサ
KR100236533B1 (ko) * 1997-01-16 2000-01-15 윤종용 배럴 쉬프터와 산술논리 연산기가 연결되어 있는 디지탈 신호 처리기 및 그 오버플로 검출방법
US7206800B1 (en) * 2000-08-30 2007-04-17 Micron Technology, Inc. Overflow detection and clamping with parallel operand processing for fixed-point multipliers
US6912560B2 (en) * 2000-12-08 2005-06-28 Agere Systems, Inc. Adder with improved overflow flag generation
US6947962B2 (en) * 2002-01-24 2005-09-20 Intel Corporation Overflow prediction algorithm and logic for high speed arithmetic units
US7454455B2 (en) * 2004-06-07 2008-11-18 International Business Machines Corporation Apparatus, and system, for efficient and reliable computation of results for mathematical functions

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5674774A (en) * 1979-11-22 1981-06-20 Nec Corp Arithmetic circuit with overflow detector
US4578750A (en) * 1983-08-24 1986-03-25 Amdahl Corporation Code determination using half-adder based operand comparator
FR2559285B1 (fr) * 1984-02-03 1986-04-25 Efcis Unite arithmetique et logique avec indicateur de debordement
JPS61239327A (ja) * 1985-04-16 1986-10-24 Nec Corp オ−バフロ−検出方式
JPH0776911B2 (ja) * 1988-03-23 1995-08-16 松下電器産業株式会社 浮動小数点演算装置
US4941119A (en) * 1988-11-30 1990-07-10 Control Data Corporation Method and apparatus for predicting an overflow in an integer multiply

Also Published As

Publication number Publication date
EP0520378A2 (de) 1992-12-30
JP2894015B2 (ja) 1999-05-24
CA2072265A1 (en) 1992-12-29
DE69227482T2 (de) 1999-06-24
US5260890A (en) 1993-11-09
EP0520378B1 (de) 1998-11-04
JPH0511980A (ja) 1993-01-22
EP0520378A3 (en) 1993-06-23
CA2072265C (en) 1997-12-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee