DE69224649T2 - Speichereinheit mit mehrfach schreibbarem cachespeicher - Google Patents

Speichereinheit mit mehrfach schreibbarem cachespeicher

Info

Publication number
DE69224649T2
DE69224649T2 DE69224649T DE69224649T DE69224649T2 DE 69224649 T2 DE69224649 T2 DE 69224649T2 DE 69224649 T DE69224649 T DE 69224649T DE 69224649 T DE69224649 T DE 69224649T DE 69224649 T2 DE69224649 T2 DE 69224649T2
Authority
DE
Germany
Prior art keywords
storage unit
writable cache
multiple writable
cache
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69224649T
Other languages
English (en)
Other versions
DE69224649D1 (de
Inventor
James Maino
Stanley Naddeo
Charles Snell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Publication of DE69224649D1 publication Critical patent/DE69224649D1/de
Application granted granted Critical
Publication of DE69224649T2 publication Critical patent/DE69224649T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69224649T 1991-11-04 1992-11-03 Speichereinheit mit mehrfach schreibbarem cachespeicher Expired - Fee Related DE69224649T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US78758491A 1991-11-04 1991-11-04
PCT/US1992/009417 WO1993009497A2 (en) 1991-11-04 1992-11-03 Memory unit including a multiple write cache

Publications (2)

Publication Number Publication Date
DE69224649D1 DE69224649D1 (de) 1998-04-09
DE69224649T2 true DE69224649T2 (de) 1998-06-25

Family

ID=25141954

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69224649T Expired - Fee Related DE69224649T2 (de) 1991-11-04 1992-11-03 Speichereinheit mit mehrfach schreibbarem cachespeicher

Country Status (5)

Country Link
EP (1) EP0611462B1 (de)
JP (1) JPH07500936A (de)
KR (1) KR940703050A (de)
DE (1) DE69224649T2 (de)
WO (1) WO1993009497A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2292822A (en) * 1994-08-31 1996-03-06 Hewlett Packard Co Partitioned cache memory
WO2001038970A2 (en) * 1999-11-22 2001-05-31 Ericsson Inc Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks
US6745293B2 (en) 2000-08-21 2004-06-01 Texas Instruments Incorporated Level 2 smartcache architecture supporting simultaneous multiprocessor accesses
EP1215581A1 (de) 2000-12-15 2002-06-19 Texas Instruments Incorporated Cache-Speicherzugriffs-Anordnung und Verfahren

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4208716A (en) * 1978-12-11 1980-06-17 Honeywell Information Systems Inc. Cache arrangement for performing simultaneous read/write operations
US4381541A (en) * 1980-08-28 1983-04-26 Sperry Corporation Buffer memory referencing system for two data words

Also Published As

Publication number Publication date
EP0611462B1 (de) 1998-03-04
WO1993009497A3 (en) 1993-08-05
DE69224649D1 (de) 1998-04-09
JPH07500936A (ja) 1995-01-26
WO1993009497A2 (en) 1993-05-13
EP0611462A1 (de) 1994-08-24
KR940703050A (ko) 1994-09-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee