AU7728300A - Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks - Google Patents

Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks

Info

Publication number
AU7728300A
AU7728300A AU77283/00A AU7728300A AU7728300A AU 7728300 A AU7728300 A AU 7728300A AU 77283/00 A AU77283/00 A AU 77283/00A AU 7728300 A AU7728300 A AU 7728300A AU 7728300 A AU7728300 A AU 7728300A
Authority
AU
Australia
Prior art keywords
buffer memories
seperate
buffering
tasks
systems
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU77283/00A
Inventor
Paul W. Dent
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ericsson Inc
Original Assignee
Ericsson Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Inc filed Critical Ericsson Inc
Publication of AU7728300A publication Critical patent/AU7728300A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
AU77283/00A 1999-11-22 2000-09-28 Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks Abandoned AU7728300A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US44708199A 1999-11-22 1999-11-22
US09447081 1999-11-22
PCT/US2000/026669 WO2001038970A2 (en) 1999-11-22 2000-09-28 Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks

Publications (1)

Publication Number Publication Date
AU7728300A true AU7728300A (en) 2001-06-04

Family

ID=23774937

Family Applications (1)

Application Number Title Priority Date Filing Date
AU77283/00A Abandoned AU7728300A (en) 1999-11-22 2000-09-28 Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks

Country Status (2)

Country Link
AU (1) AU7728300A (en)
WO (1) WO2001038970A2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8812706B1 (en) 2001-09-06 2014-08-19 Qualcomm Incorporated Method and apparatus for compensating for mismatched delays in signals of a mobile display interface (MDDI) system
US7062606B2 (en) * 2002-11-01 2006-06-13 Infineon Technologies Ag Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events
GB2401748B (en) * 2003-05-14 2005-04-13 Motorola Inc Apparatus and method of memory allocation therefor
ATE509459T1 (en) 2003-06-02 2011-05-15 Qualcomm Inc GENERATION AND IMPLEMENTATION OF A SIGNAL PROTOCOL AND INTERFACE FOR HIGHER DATA RATES
KR101178080B1 (en) 2003-08-13 2012-08-30 퀄컴 인코포레이티드 A signal interface for higher data rates
CN101764804A (en) 2003-09-10 2010-06-30 高通股份有限公司 High data rate interface
EP2244437B1 (en) 2003-10-15 2013-09-04 Qualcomm Incorporated High data rate interface
CA2775734C (en) 2004-03-10 2014-01-07 Qualcomm Incorporated High data rate interface apparatus and method
US8650304B2 (en) 2004-06-04 2014-02-11 Qualcomm Incorporated Determining a pre skew and post skew calibration data rate in a mobile display digital interface (MDDI) communication system
WO2006016298A1 (en) * 2004-08-03 2006-02-16 Koninklijke Philips Electronics N.V. Controller and a method of for controlling the communication between a processor and an external peripheral device
US8873584B2 (en) 2004-11-24 2014-10-28 Qualcomm Incorporated Digital data interface device
US8699330B2 (en) 2004-11-24 2014-04-15 Qualcomm Incorporated Systems and methods for digital data transmission rate control
US8539119B2 (en) 2004-11-24 2013-09-17 Qualcomm Incorporated Methods and apparatus for exchanging messages having a digital data interface device message format
US8692838B2 (en) 2004-11-24 2014-04-08 Qualcomm Incorporated Methods and systems for updating a buffer
US8667363B2 (en) 2004-11-24 2014-03-04 Qualcomm Incorporated Systems and methods for implementing cyclic redundancy checks
US8692839B2 (en) 2005-11-23 2014-04-08 Qualcomm Incorporated Methods and systems for updating a buffer

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2008313A1 (en) * 1989-05-03 1990-11-03 Howard G. Sachs Cache accessing method and apparatus
EP0496439B1 (en) * 1991-01-15 1998-01-21 Koninklijke Philips Electronics N.V. Computer system with multi-buffer data cache and method therefor
DE69224649T2 (en) * 1991-11-04 1998-06-25 Unisys Corp STORAGE UNIT WITH MULTIPLE WRITABLE CACHE
US5442747A (en) * 1993-09-27 1995-08-15 Auravision Corporation Flexible multiport multiformat burst buffer
US5701432A (en) * 1995-10-13 1997-12-23 Sun Microsystems, Inc. Multi-threaded processing system having a cache that is commonly accessible to each thread
EP0856797B1 (en) * 1997-01-30 2003-05-21 STMicroelectronics Limited A cache system for concurrent processes
US5930821A (en) * 1997-05-12 1999-07-27 Integrated Device Technology, Inc. Method and apparatus for shared cache lines in split data/code caches
US6260114B1 (en) * 1997-12-30 2001-07-10 Mcmz Technology Innovations, Llc Computer cache memory windowing

Also Published As

Publication number Publication date
WO2001038970A2 (en) 2001-05-31
WO2001038970A3 (en) 2002-03-07

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase