DE69224423T2 - Leitfähige Muster-Schichtstruktur und Verfahren zur Herstellung der leitfähigen Muster-Schichtstruktur - Google Patents
Leitfähige Muster-Schichtstruktur und Verfahren zur Herstellung der leitfähigen Muster-SchichtstrukturInfo
- Publication number
- DE69224423T2 DE69224423T2 DE1992624423 DE69224423T DE69224423T2 DE 69224423 T2 DE69224423 T2 DE 69224423T2 DE 1992624423 DE1992624423 DE 1992624423 DE 69224423 T DE69224423 T DE 69224423T DE 69224423 T2 DE69224423 T2 DE 69224423T2
- Authority
- DE
- Germany
- Prior art keywords
- layer structure
- conductive pattern
- pattern layer
- producing
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0154—Polyimide
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0302—Properties and characteristics in general
- H05K2201/0317—Thin film conductor layer; Thin film passive component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0597—Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S428/00—Stock material or miscellaneous articles
- Y10S428/901—Printed circuit
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28957691A JPH05129760A (ja) | 1991-11-06 | 1991-11-06 | 導体パターンの形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69224423D1 DE69224423D1 (de) | 1998-03-19 |
DE69224423T2 true DE69224423T2 (de) | 1998-07-23 |
Family
ID=17745026
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE1992624423 Expired - Fee Related DE69224423T2 (de) | 1991-11-06 | 1992-11-04 | Leitfähige Muster-Schichtstruktur und Verfahren zur Herstellung der leitfähigen Muster-Schichtstruktur |
Country Status (4)
Country | Link |
---|---|
US (2) | US5378310A (de) |
EP (1) | EP0541436B1 (de) |
JP (1) | JPH05129760A (de) |
DE (1) | DE69224423T2 (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06314880A (ja) * | 1993-04-28 | 1994-11-08 | Fujitsu Ltd | ポリイミド多層回路基板の製造方法 |
US5662788A (en) * | 1996-06-03 | 1997-09-02 | Micron Technology, Inc. | Method for forming a metallization layer |
US7126195B1 (en) | 1996-06-03 | 2006-10-24 | Micron Technology, Inc. | Method for forming a metallization layer |
US5976974A (en) * | 1997-04-22 | 1999-11-02 | W. L. Gore & Associates, Inc. | Method of forming redundant signal traces and corresponding electronic components |
JP2001223460A (ja) | 2000-02-08 | 2001-08-17 | Fujitsu Ltd | 実装回路基板及びその製造方法 |
JP4585807B2 (ja) * | 2003-12-05 | 2010-11-24 | 三井金属鉱業株式会社 | プリント配線基板の製造方法 |
JP3736806B2 (ja) * | 2003-12-26 | 2006-01-18 | 三井金属鉱業株式会社 | プリント配線基板、その製造方法および回路装置 |
JP4570390B2 (ja) * | 2004-04-26 | 2010-10-27 | 京セラ株式会社 | 配線基板及びその製造方法 |
DE102004023752B4 (de) * | 2004-05-11 | 2006-08-24 | Infineon Technologies Ag | Verfahren zur Vermeidung der Verringerung der Dicke der Umverdrahtung |
JP4652179B2 (ja) * | 2005-09-05 | 2011-03-16 | 日東電工株式会社 | 配線回路基板 |
JP4720521B2 (ja) * | 2006-01-27 | 2011-07-13 | 住友金属鉱山株式会社 | フレキシブル配線基板およびその製造方法 |
WO2011043194A1 (en) | 2009-10-09 | 2011-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
KR20120093864A (ko) | 2009-10-09 | 2012-08-23 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
KR101802406B1 (ko) | 2009-11-27 | 2017-11-28 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 반도체 장치의 제작방법 |
JP6513551B2 (ja) | 2015-10-20 | 2019-05-15 | リンナイ株式会社 | 暖房システム |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4411972A (en) * | 1981-12-30 | 1983-10-25 | International Business Machines Corporation | Integrated circuit photomask |
JPS61272746A (ja) * | 1985-05-28 | 1986-12-03 | Asahi Glass Co Ltd | フオトマスクブランクおよびフオトマスク |
MY101308A (en) * | 1986-06-09 | 1991-09-05 | Minnesota Mining & Mfg | Presensitized circuit material. |
US4770897A (en) * | 1987-05-05 | 1988-09-13 | Digital Equipment Corporation | Multilayer interconnection system for multichip high performance semiconductor packaging |
US4805683A (en) * | 1988-03-04 | 1989-02-21 | International Business Machines Corporation | Method for producing a plurality of layers of metallurgy |
US4810332A (en) * | 1988-07-21 | 1989-03-07 | Microelectronics And Computer Technology Corporation | Method of making an electrical multilayer copper interconnect |
US4964945A (en) * | 1988-12-09 | 1990-10-23 | Minnesota Mining And Manufacturing Company | Lift off patterning process on a flexible substrate |
JPH03108797A (ja) * | 1989-09-22 | 1991-05-08 | Ngk Spark Plug Co Ltd | 多層配線基板およびその製造方法 |
EP0453785A1 (de) * | 1990-04-24 | 1991-10-30 | Oerlikon Contraves AG | Verfahren zur Herstellung von mehrlagigen Dünnschichtschaltungen mit integrierten Dünnschichtwiderständen |
-
1991
- 1991-11-06 JP JP28957691A patent/JPH05129760A/ja active Pending
-
1992
- 1992-11-04 EP EP19920402978 patent/EP0541436B1/de not_active Expired - Lifetime
- 1992-11-04 DE DE1992624423 patent/DE69224423T2/de not_active Expired - Fee Related
-
1993
- 1993-11-01 US US08/143,642 patent/US5378310A/en not_active Expired - Fee Related
- 1993-12-17 US US08/168,221 patent/US5415920A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5415920A (en) | 1995-05-16 |
EP0541436B1 (de) | 1998-02-11 |
EP0541436A2 (de) | 1993-05-12 |
JPH05129760A (ja) | 1993-05-25 |
US5378310A (en) | 1995-01-03 |
DE69224423D1 (de) | 1998-03-19 |
EP0541436A3 (de) | 1994-01-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |