DE69223267T2 - Steuersystem für eine Speicherplattenanordnung - Google Patents

Steuersystem für eine Speicherplattenanordnung

Info

Publication number
DE69223267T2
DE69223267T2 DE69223267T DE69223267T DE69223267T2 DE 69223267 T2 DE69223267 T2 DE 69223267T2 DE 69223267 T DE69223267 T DE 69223267T DE 69223267 T DE69223267 T DE 69223267T DE 69223267 T2 DE69223267 T2 DE 69223267T2
Authority
DE
Germany
Prior art keywords
bus
array
enable signals
configuration error
disk array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69223267T
Other languages
English (en)
Other versions
DE69223267D1 (de
Inventor
Mahmoud K Jibbe
Craig C Mccombs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MagnaChip Semiconductor Ltd
NCR International Inc
Original Assignee
NCR International Inc
Hyundai Electronics America Inc
Symbios Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR International Inc, Hyundai Electronics America Inc, Symbios Logic Inc filed Critical NCR International Inc
Publication of DE69223267D1 publication Critical patent/DE69223267D1/de
Application granted granted Critical
Publication of DE69223267T2 publication Critical patent/DE69223267T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
DE69223267T 1991-03-14 1992-03-12 Steuersystem für eine Speicherplattenanordnung Expired - Lifetime DE69223267T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/669,554 US5430747A (en) 1991-03-14 1991-03-14 Bus configuration validation for a multiple source disk array bus

Publications (2)

Publication Number Publication Date
DE69223267D1 DE69223267D1 (de) 1998-01-08
DE69223267T2 true DE69223267T2 (de) 1998-05-28

Family

ID=24686788

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69223267T Expired - Lifetime DE69223267T2 (de) 1991-03-14 1992-03-12 Steuersystem für eine Speicherplattenanordnung

Country Status (5)

Country Link
US (1) US5430747A (de)
EP (1) EP0503936B1 (de)
JP (1) JP3562818B2 (de)
DE (1) DE69223267T2 (de)
HK (1) HK1003249A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5463753A (en) * 1992-10-02 1995-10-31 Compaq Computer Corp. Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache controller
US5448709A (en) * 1992-10-13 1995-09-05 Compaq Computer Corporation Disk array controller having command descriptor blocks utilized by bus master and bus slave for respectively performing data transfer operations
WO1994009436A1 (en) * 1992-10-13 1994-04-28 Compaq Computer Corporation Disk array controller having advanced internal bus protocol
US5727005A (en) * 1994-08-31 1998-03-10 Le; Chinh H. Integrated circuit microprocessor with programmable memory access interface types
US5790870A (en) * 1995-12-15 1998-08-04 Compaq Computer Corporation Bus error handler for PERR# and SERR# on dual PCI bus system
US6178520B1 (en) * 1997-07-31 2001-01-23 Lsi Logic Corporation Software recognition of drive removal or insertion in a storage system
US6018807A (en) * 1997-09-25 2000-01-25 Micron Electronics, Inc. Simulation "bus contention" detection
US6085333A (en) * 1997-12-19 2000-07-04 Lsi Logic Corporation Method and apparatus for synchronization of code in redundant controllers in a swappable environment
DE19826388B4 (de) * 1998-06-12 2007-01-11 Sgs-Thomson Microelectronics Gmbh Fehlerverarbeitungsschaltung für eine Empfangsstelle eines Datenübertragungssystems
US6272651B1 (en) * 1998-08-17 2001-08-07 Compaq Computer Corp. System and method for improving processor read latency in a system employing error checking and correction

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS648465A (en) * 1987-06-30 1989-01-12 Mitsubishi Electric Corp Tri-state bus circuit
US4953167A (en) * 1988-09-13 1990-08-28 Unisys Corporation Data bus enable verification logic
US4918696A (en) * 1988-09-19 1990-04-17 Unisys Corporation Bank initiate error detection

Also Published As

Publication number Publication date
JPH06180675A (ja) 1994-06-28
EP0503936A1 (de) 1992-09-16
JP3562818B2 (ja) 2004-09-08
DE69223267D1 (de) 1998-01-08
US5430747A (en) 1995-07-04
EP0503936B1 (de) 1997-11-26
HK1003249A1 (en) 1998-10-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR

8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: HYNIX SEMICONDUCTOR INC., ICHON, KYONGGI, KR

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DEL, US

8327 Change in the person/name/address of the patent owner

Owner name: MAGNACHIP SEMICONDUCTOR, LTD., CHEONGJU, KR

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DEL, US