DE69223046D1 - Integrierter CMOS-statischer RAM - Google Patents
Integrierter CMOS-statischer RAMInfo
- Publication number
- DE69223046D1 DE69223046D1 DE69223046T DE69223046T DE69223046D1 DE 69223046 D1 DE69223046 D1 DE 69223046D1 DE 69223046 T DE69223046 T DE 69223046T DE 69223046 T DE69223046 T DE 69223046T DE 69223046 D1 DE69223046 D1 DE 69223046D1
- Authority
- DE
- Germany
- Prior art keywords
- static ram
- integrated cmos
- cmos static
- integrated
- ram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP19920830383 EP0578900B1 (de) | 1992-07-16 | 1992-07-16 | Integrierter CMOS-statischer RAM |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69223046D1 true DE69223046D1 (de) | 1997-12-11 |
DE69223046T2 DE69223046T2 (de) | 1998-02-26 |
Family
ID=8212140
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE1992623046 Expired - Fee Related DE69223046T2 (de) | 1992-07-16 | 1992-07-16 | Integrierter CMOS-statischer RAM |
Country Status (2)
Country | Link |
---|---|
EP (1) | EP0578900B1 (de) |
DE (1) | DE69223046T2 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19740695C2 (de) * | 1997-09-16 | 2002-11-21 | Infineon Technologies Ag | Datenspeicher mit Mehrebenenhierarchie |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0734311B2 (ja) * | 1986-01-21 | 1995-04-12 | 株式会社東芝 | メモリセル |
US4910712A (en) * | 1988-02-18 | 1990-03-20 | Saratoga Semiconductor Corporation | Memory cell with a plurality of pass gates |
US4873665A (en) * | 1988-06-07 | 1989-10-10 | Dallas Semiconductor Corporation | Dual storage cell memory including data transfer circuits |
-
1992
- 1992-07-16 DE DE1992623046 patent/DE69223046T2/de not_active Expired - Fee Related
- 1992-07-16 EP EP19920830383 patent/EP0578900B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0578900A1 (de) | 1994-01-19 |
EP0578900B1 (de) | 1997-11-05 |
DE69223046T2 (de) | 1998-02-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |