DE69216785T2 - Control circuit for a display unit with digital source control for generating multi-level control voltages from a single external energy source - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the invention

The invention relates to a display unit driving circuit, and more particularly, it relates to a digital source electrode driver for outputting control voltages of multiple levels for displaying an image of multiple gray levels based on an input digital video signal of a specified number of bits.

2. Description of the state of the art

Fig. 13 schematically shows a conventional matrix liquid crystal display unit. This matrix liquid crystal display unit uses a TFT (thin film transistor) as a switching element for driving pixel electrodes. A TFT liquid crystal display panel 300 includes m signal electrodes 302 (Nos. O1 to Om) arranged in parallel with each other and i scanning electrodes 301 (Nos. 1 to i) arranged in parallel with each other and perpendicular to the signal electrodes 302. Near the intersection point between each scanning electrode 301 and each signal electrode 302, a TFT 304 for driving a corresponding pixel electrode 303 is provided. A horizontal scanning line consists of m pixel electrodes 303 connected to a scanning electrode 301.

The TFT liquid crystal panel 300 is driven by a driver circuit 200 for the LCD unit with a source driver 201 and a gate driver 202. The source driver 201 and the gate driver 202 are connected to the signal electrodes 302 and the scanning electrodes 301, respectively. The source driver 301 samples and holds an input digital image or video signal to supply the signal to the signal electrodes 302. On the other hand, the gate driver 202 sequentially outputs scanning pulses to the scanning electrodes 301. The gate driver 202 and the source driver 201 receive control signals such as a clock signal from a control circuit 203. An external supply voltage generating circuit 204 generates a plurality of external supply voltages of different levels (e.g., eight) from an input supply voltage and supplies them to the source driver 201.

Fig. 14 shows the structure of the source driver 201 shown in Fig. 13 in detail. The source driver 201 includes a shift register 101, a sampling memory 102, a latch 103, a decoder 104 and an output voltage selection circuit 105. The source driver 201 has m signal systems corresponding to the m signal electrodes.

Fig. 15 shows the structure of the signal system n (1 ≤ n ≤ m) of the source driver 201. As shown in Fig. 15, the part belonging to the signal system n of the output voltage selection circuit 105 is composed of eight analog switches ASW₀ to ASW₇. In operation, the shift register 101 shown in Figs. 13 and 14 outputs a sampling pulse Tsmpn for the pixel n. At the leading edge of the sampling pulse Tsmpn, externally input video signals D₀, D₁ and D₂ are taken into the sampling memory 101 and maintained in three D flip-flops 121, 122 and 123 belonging to the signal system n of the sampling memory 102. When the sampling operation for one horizontal period is completed, an output pulse OE are input to the latch 103. In response to this pulse OE, the video signals D 0 , D 1 , and D 2 held in the sampling latch 102 are transferred to the latch 103 (three D flip-flops 131, 132, and 133) and then to the decoder 104. The decoder 104 decodes the input video signals D 0 , D 1 , and D 2 and outputs eight enable signals Y 0 to Y 7 (only one of these signals is at a high level (H), while the others are at a low level (L)). Depending on the contents of the enable signals Y 0 to Y 7 , one of the analog switches ASW 0 to ASW 7 in the output voltage selection circuit 105 becomes conductive. Therefore, of the eight external power supply voltages V 0 to V 1 , V 2 , V 3 , V 4 , V 5 , V 6 , V 7 , V 8 , V 9 , V 10 , V 20 , V 30 , V 40 , V 50 , V 60 , V 70 , V 80 , V 90 , V 10 , V 11 , V 21 , V 32 , V 40 , V 51 , V 62 , V 73 , V 80 , V 90 , V 11 , V 12 , V 21 , V 32 , V 40 , V 51 , V 62 , V 73 , V 80 , V 90 , V 10 , V 11 , V 21 , V 32 , V 40 , V 51 , V 62 , V 73 , V 80 , V 10 , V 11 , V 21 , V 32 , V to V₇ transmitted from the external power supply voltage generating circuit 204 to the output voltage selecting circuit 105, the voltage applied to the analog switch turned on is output to the signal electrode (source line) On (1 ≤ n ≤ m). In this way, the external power supply voltages V₀ to V₇ having different levels or gradations can be supplied to the TFT liquid crystal panel 300 as driving voltages depending on the contents of the video signals D₀, D₁ and D₂.

However, when the number of bits of the video signal is increased in order to improve the reproducibility of images with multiple gray levels, the above-mentioned conventional driving circuit has a problem in that an increased number of external power supply voltages serving as reference voltages for brightness scaling are required. When the number of bits of the video signal increases to, for example, 3, 4, 6, 8, ..., the number of external power supply voltages increases to 2³(= 8), 2⁴(= 16), 2⁶(= 64), 2⁸(= 256), ... Therefore, the following problems arise:

(1) The dimensions of the external power source increase, which leads to an increase in cost.

(2) An LSI (Large-Scale Integrated) circuit incorporating the above source driver is required to have an increased number of input terminals, making it difficult to accommodate the LSI circuit.

(3) The external supply voltages must have higher accuracy, which leads to difficulties in controlling voltage adjustment operations.

Document EP-A-0 298 255 discloses a driver circuit for an active matrix liquid crystal (LC) display panel in which a control voltage is periodically converted from a value corresponding to the ON state of the LC elements to a value corresponding to the OFF state thereof during a horizontal scanning period. Analog switches connected to the source lines of the panel are switched at the beginning of each horizontal scanning period. Thereafter, each source line is charged until a voltage corresponding to its respective digital data signal sample is reached, and then the respective analog switch is switched off. Thereafter, the voltage is maintained by the capacitance of the source line and/or an additional sample holding device.

SUMMARY OF THE INVENTION

The invention is based on the object of providing a display unit driver circuit which can provide drive voltages with multiple levels corresponding to multiple gray levels of an image to be displayed without increasing the number of external voltage sources.

To achieve this object, the invention provides the display unit driving circuit defined by claim 1.

Dependent claims 2 to 6 are directed to embodiments of the invention.

A display unit driving circuit according to an embodiment of the invention operates as follows. First, a timing signal generating circuit generates timing signals having different pulse widths within each horizontal period. The number of timing signals (e.g., 8) depends on the brightness levels of the image to be displayed. One of the timing signals is always kept at H level. Then, a voltage control circuit receives video signals and the timing signals, and selects one of the timing signals based on the video signals in each horizontal period. Fig. 9 shows an example of selection of the timing signal for generating the control signal. As shown in Fig. 9, the timing signal T₀ is selected when the video signals indicated by D₀, D₁, and D₂ represent L, L, and L levels, respectively. When the video signals D₀, D₁, and D₂ represent L, L, and L levels, respectively, the timing signal T₀ is selected. When the video signals D0, D1 and D2 represent the levels H, L and L, respectively, the timing signal T1 is selected. When the video signals D0, D1 and D2 represent the levels H, H and H, respectively, the timing signal T7 is selected. Then, the voltage control circuit outputs a high-level control signal for a period corresponding to the pulse width of the selected timing signal. In the output voltage generating circuit, at the time the control signal is output in each horizontal period, the capacitor receives the external power supply voltage through the first switching means from an external voltage source so that a drive voltage is generated in each horizontal period. The external power supply voltage is supplied by an external power supply which provides an electric potential which becomes higher with the passage of time, as illustrated in Fig. 10, which shows the relationship between the timing signals and the drive circuits as shown in Fig. 10. be used in an embodiment of the invention; accordingly, the level of the driver circuit is adjustable depending on the pulse width of the selected timing signal, so that driver voltages with multiple levels can be generated.

According to the above-mentioned display unit driving circuit, multiple-level driving voltages can be generated by means of a single external power source. When the bit number of the video signal is increased to promote a multi-gray level display to improve the picture quality, the timing signal generating circuit generates an increased number of timing signals depending on the number of gray levels. The number of driving voltages increases accordingly. The above arrangement eliminates any increase in the number of external power sources. More specifically, multiple-level driving voltages can be generated without increasing the external power source. Accordingly, the following advantages are provided:

(1) The size of the external power source can be reduced, which is accompanied by a cost reduction.

(2) An LSI (Large-Scale Integrated) circuit incorporating the above source driver can have a reduced number of input terminals. This facilitates the design of the LSI.

(3) There are reduced accuracy requirements for the external supply voltage, which facilitates the setting of the external supply voltage.

According to the invention, the above-mentioned output voltage generating circuit comprises two capacitors which are alternately charged with the external power supply voltage in alternate horizontal periods, and the driving circuits are alternately output from the two capacitors. In other words, when one of the capacitors is charged, the other capacitor outputs the drive voltage. Therefore, a continuous output of the drive voltage is achieved. In one embodiment, the two capacitors are switched by output switching signals generated by the timing signal generating circuit. The output switching signals have opposite levels in their active periods, and they are respectively reversed in each horizontal period.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram of a matrix liquid crystal display (TFT-LCD) unit having a drive circuit with a gate driver and a source driver according to an embodiment of the invention;

Fig. 2 is a block diagram of the overall system of the source driver of Fig. 1;

Fig. 3 is a diagram showing the structure of a part that processes a single signal group in the source driver;

Fig. 4 is a diagram showing a timing signal generating circuit which is a constituent of the source driver ;

Fig. 5 is a timing chart showing output waveforms of the timing signal generating circuit which is a constituent of the source driver;

Fig. 6 is a timing chart of other output waveforms of the timing signal generating circuit;

Fig. 7 is a diagram for explaining a flow of generating control signals in a voltage control circuit, which is part of the source driver;

Fig. 8 is a timing diagram of alternative, exemplary output waveforms of the timing signal generating circuit;

Fig. 9 is a diagram for explaining a procedure for generating a control signal based on the contents of input digital video signals according to the invention;

Fig. 10 is a graph showing the relationship between the timing signals and the driving voltages;

Fig. 11 is a characteristic curve showing the relationship between applied voltages and transmittance of a normally bright liquid crystal device;

Fig. 12 is a voltage-time characteristic curve for correcting an external supply voltage;

Fig. 13 is a block diagram of a conventional matrix liquid crystal display (TFT-LCD) unit;

Fig. 14 is a block diagram of the entire system of a conventional source driver used in the conventional liquid crystal display unit of Fig. 13; and

Fig. 15 is a diagram showing a part that processes a single signal group in the source driver shown in Fig. 14.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Fig. 1 is a block diagram of a matrix liquid crystal display unit, which uses a driver circuit 200 having a gate driver 202 identical to that of Fig. 13 and employs a source driver according to an embodiment of the invention. In Fig. 1, the same components as those of Fig. 13 showing a conventional matrix liquid crystal display unit are designated by the same numerals, and no detailed description of these components will be given here. It should be noted, of course, that the liquid crystal display unit of Fig. 1 does not have a circuit for generating a plurality of external power supply voltages having a plurality of levels, such as the external power supply voltage generating circuit 204 shown in Fig. 13.

Fig. 2 shows the structure of the entire source driver 7 shown in Fig. 1. Fig. 3 shows a part of the source driver 7 which processes the n-th (1 ≤ n ≤ m) of the m signal groups (each represented by three bits). The m signal groups correspond to the m pixels. The source driver 7 includes a shift register 1, a sampling memory 2, a holding memory 3, a timing signal generating circuit 4, a voltage control circuit 5 and an output voltage generating circuit 6. The shift register 1, the sampling memory 2 and the holding memory 3 correspond to the shift register 101, the sampling memory 102 and the holding memory 103 shown in Figs. 13-15, respectively.

The timing signal generating circuit 4 consists of two parts 4A and 4B, as shown in Fig. 4. The part 4A consists of D flip-flop circuits 41, 42 and 43, an AND circuit 44, a NOR circuit 45 and a NAND circuit 47. As shown in Fig. 5, the part 4A of the timing signal generating circuit 4, when it clock pulses CLK and pulse signal OE input once in one horizontal period, output signal switching signals OE1 and OE2 which are at opposite levels in their active periods and which are respectively inverted every horizontal period, and a clear signal CLR1 obtained by inverting most of the pulse signal OE. Note that the signals OEA and OEB in Fig. 5 are output signals of the D flip-flop circuits 42 and 43, respectively.

On the other hand, the part 48 of the timing signal generating circuit 4 is composed of a 6-bit counter 46, an inverter 48 and D flip-flop circuits 49 to 55 as shown in Fig. 4. When the part 48 receives the clock pulses CLK, it first generates a signal 64CK representing 64 clock pulses as shown in Fig. 6. Then, based on the signal 64CK, eight kinds (corresponding to the number of gray levels of an image) of timing signals T₀, T₁, ..., T₇ having different pulse widths are generated in one horizontal period. (Note that the timing signal T₀ is kept at the H level.)

The voltage control circuit 5, more specifically the part thereof which processes the signal group n shown in Fig. 3, receives video signals HnD₀, HnD₁ and HnD₂ from the latch 3, the timing control signals T₀, T₁, ..., T₇ and the output signal switching signals OE1 and OE2 from the timing control signal generating circuit 4. Then, the voltage control circuit 5 outputs output control signals CON1 and CON2 for each horizontal period at specific levels depending on the contents of the received signals and the output signal switching signals, as shown in Fig. 7. More specifically, when the output signal switching signals OE1 and OE2 represent logic "1" and logic "0", respectively, the control signal CON1 is output for a period corresponding to the pulse width of the control signal T₀, T₁, ..., or T₇ selected depending on the contents of the video signals HnD₀, HnD₁, and HnD₂ is maintained at the H level. Meanwhile, the control signal CON2 is maintained at the L level regardless of the contents of the video signals HnD₀, HnD₁, and HnD₂. When the output signal switching signals OE1 and OE2 represent logic "0" (corresponding to the L level) and logic "1" (corresponding to the H level), respectively, the control signal CON1 takes the L level regardless of the contents of the video signals HnD₀, HnD₁, and HnD₂. Meanwhile, the control signal CON2 is maintained at the L level for a period corresponding to the pulse width of the timing signal T₀, T₁, ..., or T₇ selected depending on the contents of the video signals HnD₀, HnD₁, and HnD₂. is maintained at the H level as selected depending on the contents of the video signals HnD₀, HnD₁ and HnD₂. When the output signal switching signals OE1 and OE2 both represent logic "0", the control signals CON1 and CON2 are switched to the "L" level regardless of the contents of the video signals HnD₀, HnD₁ and HnD₂. Note that there is no case where both the signals OE1 and OE2 represent logic "1" as shown in Fig. 5.

As shown in Fig. 3, the output voltage generating circuit 6 (more specifically, its part that processes the signal group n) is composed of wirings L1 and L2 connecting an external voltage source (voltage V) to a source line (signal electrode) On, capacitors C1 and C2 connected between each of the wirings L1 and L2 and ground, and analog switches ASW1, ASW2, ASW3, and ASW4. The analog switches ASW1 and ASW3 are arranged in the wiring L1 and in opposite sides of the capacitor C1 to the external voltage source and the source line On, respectively. These analog switches ASW1 and ASW3 are turned on and off (the switches are turned on when each control signal is at H level, and they are turned off when each control signal is at L level). On the other hand, the analog switches ASW2 and ASW4 are arranged in the wiring L2 and to the external voltage source and the source line (signal electrode) On from the capacitor C2, respectively. These switches ASW2 and ASW4 are turned on and off depending on the control signal KON2 from the voltage control circuit 5 and the output signal switching signal OE1 from the timing signal generating circuit 4 (the switches are turned on when each control signal is at H level, and they are turned off when each control signal is at L level).

The above-mentioned source driver 7 operates as follows. First, when the shift register 1 outputs a sampling pulse Tsmpn for the pixel n, the externally input video signals D�0, D₁ and D₂ are taken into the sampling memory 2 at the leading edge of the sampling pulse Tsmpn. Then, these sampled video signals are held as video signals SnD�0, SnD₁ and SnD₂ in the three D flip-flops 21, 22 and 23 of the sampling memory 2 (part which processes the signal group n). When the sampling operation for one horizontal period is completed, the pulse signal OE is input to the latch 3. In response to the pulse signal OE, the video signals SnD�0, SnD₁ and SnD₂ held in the sampling memory 2 are from the latch 3 (three D flip-flops 31, 32 and 33) to be then transmitted to the voltage control circuit 5 as video signals HnD�0, HnD�1 and HnD₂. The voltage control circuit 5 outputs the control signal CON1 or CON2 of H level for the period corresponding to the pulse width of the timing signal T�0, T�1, ... or T₇ selected in each horizontal period based on the contents of the video signals HnD�0, HnD₁ and HnD₂ as described above. Now, assume that that in a specific horizontal period, the output signal switching signal OE1 is at the H level and the output signal switching signal OE2 is at the L level. In this case, the control signal CON1 is switched to the H level and the control signal CON2 is switched to the L level. Accordingly, in the output voltage generating circuit 6, the analog switches ASW1 and ASW4 are turned on while the analog switches ASW2 and ASW3 are turned off. Therefore, the capacitor C1 is charged via the analog switches ASW1 for a period with the external power supply voltage V corresponding to the pulse width of the timing signal T₀, T₁, ... or T₇ as selected by the voltage control circuit 5. At this time, by supplying the external power supply voltage V from an external voltage source having a potential which becomes higher with the lapse of time as shown in Fig. 10, a drive voltage corresponding to the content of the video signals D₀, D₁, ... is generated. and D₂ is generated between the electrodes of the capacitor C1. On the other hand, a voltage to which the capacitor C2 has been charged in the preceding horizontal period is output therefrom to the source line (signal electrode) On via the analog switch ASW4.

As can be seen from the above, the output signal switching signals OE1, OE2 serve to determine which of the capacitors C1, C2 should be charged with the external supply voltage and which of the voltages to which the capacitors C1, C2 have been charged should be supplied to the source line On.

In the next horizontal period, the output signal switching signal OE1 is switched to the L level, and the output signal OE2 is switched to the H level. In this case, the control signal CON1 is switched to the L level, and the control signal CON2 is switched to the H level.

By these changes in the voltage state, the analog switches ASW1 and ASW4 are turned off while the analog switches ASW2 and ASW3 are turned on, both in the output voltage generating circuit 6. Therefore, the capacitor C2 is charged with the external power supply voltage V through the analog switch ASW2 for a period corresponding to the pulse width of the timing signal T0, T1, ... or T7 as selected by the voltage control circuit 5. At this time, since an external power supply voltage V is supplied from the external power source and the potential of the voltage becomes higher with the passage of time as shown in Fig. 10, a driving voltage of the level corresponding to the content of the video signals D0, D1 and D2 is generated between the electrodes of the capacitor C2.

On the other hand, a voltage corresponding to the voltage (drive voltage) charged in the previous horizontal period is output from the capacitor C1 to the source line On via the analog switch ASW3. As is apparent from the above, while one capacitor is being charged, the other capacitor can output a drive voltage, so that drive voltages of multiple levels are continuously output from the output voltage generating circuit 6. Although there is a moment at a transition from one horizontal period to another in which the output signal switching signals OE1 and OE2 are both at the L level and the control signals CON1 and CON2 are both at the L level (the analog switches ASW1 and ASW4 are all in the off state), almost no influence is exerted on the above-mentioned operation in each horizontal period.

As described above, the source driver 7 can generate multi-level drive voltages with a single external voltage source. When the bit number of the video signal is increased to increase the number of gray levels of an image, increase, the timing signal generating circuit 4 generates an increased number of timing signals corresponding to the number of gray levels to enable generation of multi-level drive voltages based on the timing signals. In this way, multi-level drive signals can be supplied without increasing the number of external voltage sources.

When a liquid crystal display panel that is bright in the normal state is used as the display panel 300, the light transmittance varies in the middle voltage region and is saturated in the low and high voltage regions, as shown in Fig. 11. Since a 1-bit digital display system only displays the on and off states, high contrast can be achieved as long as the display panel is operated with voltages in the low and high voltage regions. However, in a multi-gray level display system, since the light transmittance in the low and high voltage regions changes nonlinearly with respect to the applied voltage V, the intended brightness cannot be achieved without modifying the applied voltage V, resulting in failure to display correct colors. Therefore, the characteristic curve (voltage-time characteristic) of the external supply voltage shown in Fig. 10 is corrected as shown in Fig. 12 to provide voltage levels or gradations with linear characteristics.

It is noted here that although the transmittance changes in the medium voltage range as shown in Fig. 11 at present, the transmittance must change in the low voltage range in the future because then a liquid crystal display can be used using a low drive voltage such as 3 V.

The invention may be embodied in other specific forms without departing from its scope as defined by the claims.

Claims (6)

1. Control circuit for a display unit, which is designed to generate, by means of an external voltage source which supplies a time-varying voltage output signal, a plurality of output voltage signals for controlling the display intensity of pixel elements of a matrix display panel (300), each output voltage signal having a level corresponding to a selected one of a number of predetermined display intensities, depending on an input digital video signal (D�0, D�1, D�2) which represents the image to be displayed, with: - a device (4) for generating a number of timing signals (T₀ - T₇) of different widths, the number of which corresponds to the number of display intensities; - means (5) for selecting one of the timing signals in accordance with the level of the video signal and for generating therefrom a control signal which is generated in successive horizontal periods alternately as a first and second control signal (CON1, CON2); and - means (6) for generating the plurality of output voltage signals, comprising means (ASW1 - 4) for connecting the external voltage source to a first capacitor (C1) or a second capacitor (C2) for a predetermined period in response to the first or second control signal, respectively, in such a way that when one of the two capacitors is connected to the external voltage source, the other capacitor provides the output voltage signal. 2. A control circuit for a display unit according to claim 1, wherein the timing signal generating means (4) further generates first and second output signal switching signals (OE1, OE2) which, in their active periods have opposite levels to each other and which are respectively inverted every horizontal period, wherein the selecting means (5) receives the video signal (D₀, D₁, D₂), the timing signals (T₀ - T₇) and the output signal switching signals (OE1, OE2) in each horizontal period and selects one of the timing signals based on the contents of the video signal and the output signal switching signals to output the first or second control signal (CON1, CON2) of a specific level for the time corresponding to the pulse width of the selected timing signal (T₀ - T₇). 3. Control circuit for a display unit according to claim 1 or claim 2, wherein the output voltage generating means (6) comprises a first switching means (ASW1, ASW2) for supplying the first and second control signals (CON1, CON2) to the first and second capacitors (C1, C2) respectively. 4. Control circuit for a display unit according to claim 3, wherein the output voltage generating means (6) comprises a second switching means (ASW3, ASW4) for alternately outputting the output voltage signal from the first and second capacitors (C1, C2). 5. A control circuit for a display unit according to claim 4, depending on claim 2, wherein the second switching device (ASW3, ASW4) is controlled based on the states of the first and second output signal switching signals (OE1, OE2). 6. Control circuit for a display unit according to one of the preceding claims, in which the waveform of the voltage output from the external voltage source is designed so that a non-linearity of the applied voltage transmittance characteristic of the liquid crystal material used in the display panel (300) is corrected.