CN102842278B - Gate drive circuit unit, gate driver circuit and display - Google Patents
Gate drive circuit unit, gate driver circuit and display Download PDFInfo
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- CN102842278B CN102842278B CN201210277113.7A CN201210277113A CN102842278B CN 102842278 B CN102842278 B CN 102842278B CN 201210277113 A CN201210277113 A CN 201210277113A CN 102842278 B CN102842278 B CN 102842278B
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Abstract
This application discloses a kind of gate drive circuit unit, gate driver circuit and a kind of display, wherein gate drive circuit unit comprises: load module, under the control of forward scan control signal and reverse scan control signal, receive input signal from signal input part, control driver module and open or turn off; Driver module, under the control of load module, transfers to signal output part by the first clock signal; Low level maintains module, for by the current potential of stable output signal at the first voltage source.The present invention can realize the bi-directional drive function of two-way gate driver circuit under the control of forward, reverse scan control signal, and the utilization factor of circuit module is all 100%, and structure is simplified, and adopts less transistor namely to achieve bilateral scanning function.
Description
Technical field
The present invention relates to a kind of display, particularly relate to a kind of two-way gate drive circuit unit of display and two-way gate driver circuit.
Background technology
Thin film transistor (TFT) (TFT) flat pannel display (Flat Panel Display, FPD) technology is the main flow of current display technique.In recent years, integrated gate driver technology causes the broad interest of FPD industrial community.This method gate driver circuit is integrated on display base plate (as glass), quantity and the press seal operation thereof of peripheral driver chip can be reduced, the cost of FPD is reduced, can make that quality is light, thickness is thin and the narrow frame panel of outward appearance symmetry is achieved, display module is more compact, reliable simultaneously; Be conducive to the design simplifying source electrode drive circuit, improve the resolution of display panel, increase the possibility realizing flexible display panels.
Usually, integrated gate drive circuitry technology adopts unidirectional gate driver circuit, namely gated sweep pulse can only be delivered to the gate line of large sequence number in turn from the gate line of little sequence number, or gated sweep pulse is delivered to the gate line of little sequence number in turn from the gate line of large sequence number, thus view data is delivered in all row pixels be unlocked in turn line by line.Two-way gate driver circuit then has two kinds of mode of operations, in turn gated sweep pulse can not only be delivered to the gate line of large sequence number from the gate line of little sequence number, and in turn gated sweep pulse can be delivered to the gate line of little sequence number from the gate line of large sequence number.Therefore, two-way gate driver circuit has following advantage: can carry out to change neatly the scanning sequency of sweep trace as required to realize 180 degree of mirror images of image on the one hand, thus strengthens the operation likability of user; On the other hand, the periphery configure showing module can also be made more flexible.
In order to realize two-way gate driver circuit, mostly adopting two cover sweep circuits in current document, and determining direction of scanning by control signal: forward scan or reverse scan.Such as, when a set of sweep circuit in conventional two-way gate driver circuit is activated and is in forward scan, another set of sweep circuit then quits work; Vice versa.So this traditional two-way gate driver circuit exists a large amount of idle transistors, circuit larger, the chip area occupied is very large.On the other hand, the display of high resolving power, narrow frame requires that integrated gate drive circuitry is more simplified, area occupied is less.Therefore conventional two-way gate driver circuit is not suitable in the display application of high resolving power, narrow frame.In addition, conventional TFT, such as non-crystalline silicon tft, oxide TFT etc., after working long hours, its electric property can be degenerated, and such as threshold voltage drifts about, so the life-span of conventional two-way gate driver circuit is shorter.
Therefore, the bilateral scanning function how effectively realizing gate driver circuit when less transistor is a problem demanding prompt solution.
Summary of the invention
The main technical problem to be solved in the present invention is, provides the two-way gate drive circuit unit that a kind of structure is simplified.
According to a first aspect of the invention, a kind of two-way gate drive circuit unit is provided, comprise load module, driver module, low level maintenance module, forward scan control signal input end, reverse scan control signal input end and signal output part, described forward scan control signal input end is for inputting forward scan control signal, and described reverse scan control signal input end is for inputting reverse scan control signal; Described signal output part is for exporting gated sweep signal.
The control end of described driver module is coupled to the first Controlling vertex, and input end is for inputting the first clock signal, and output terminal is coupled to signal output part, and the first clock signal, under the control of the first Controlling vertex, is applied to signal output part by described driver module.
Described load module comprises the first switch module and second switch module, described first switch module comprises the first signal input part and secondary signal input end, described first signal input part is for receiving the first pulse signal of input, described secondary signal input end is coupled to forward scan control signal input end, described second switch module comprises the 3rd signal input part and the 4th signal input part, described 3rd signal input part is for receiving the second pulse signal, described 4th signal input part is coupled to reverse scan control signal input end, the output terminal of described first switch module and the output terminal of second switch module are connected respectively to the first Controlling vertex Q, charge or discharge are carried out to the first Controlling vertex, to control unlatching or the shutoff of driver module, described forward scan control signal, reverse scan control signal, the first pulse signal, the second pulse signal and the first clock signal are configured to: during forward scan, described forward scan control signal is high level, described reverse scan control signal is low level, when described first pulse signal arrives, described first clock signal is low level, after described first pulse signal becomes the low level T/3 time, described first clock signal becomes high level, the time of the delayed described first pulse signal 4T/3 of described second pulse signal, during reverse scan, described reverse scan control signal is high level, described forward scan clock control signal is low level, when described second pulse signal arrives, described first clock signal is low level, after described second pulse signal becomes the low level T/3 time, described first clock signal becomes high level, the time of the delayed described second pulse signal 4T/3 of described first pulse signal, described first clock signal is the cycle is T, dutycycle is the clock signal of 33%, and the pulsewidth of the first pulse signal and the second pulse signal is T/3, wherein T>0.
Described low level maintains module and the first Controlling vertex and signal output part is stabilized in low level, after the first Controlling vertex is discharged, described low level maintains module and the first Controlling vertex and signal output part is coupled to low level until next first Controlling vertex is charged.
Described first pulse signal is identical with frame-scan period with the cycle of the second pulse signal.
According to a further aspect in the invention, the invention also discloses a kind of gate driver circuit, comprise the gate drive circuit unit of N level cascade, gate drive circuit unit described at least one is gate drive circuit unit as above, first signal input part of n-th grade of gate drive circuit unit is coupled to the signal output part of the n-th-2 grades gate driver circuits, 3rd signal input part of the gate drive circuit unit of n-th grade is coupled to the signal output part of the n-th+2 stage drive circuit unit, wherein N be greater than 0 integer, n is the integer being greater than 0 and being less than N.
In addition, the invention also discloses a kind of display, comprising: display panel, described display panel is manufactured with the gate line of first direction and the data line of second direction; Gate driver circuit as above, in described gate driver circuit, the signal output part of drive element of the grid is coupled to the gate line corresponding with it.
The beneficial effect of the application is embodied in: by load module, driver module, the low level maintenance module of multiplexing two-way gate drive circuit unit, namely forward scan or reverse scan all adopt identical circuit module, thus under forward or reverse scan pattern, the utilization factor of circuit module is 100%.And by the cooperation of sequential, utilize single driving tube (third transistor T
3) pull-up and drop-down that outputs signal can be realized, without the need to arranging the lower trombone slide of output signal, further reducing the transistor size of two-way gate drive circuit unit, adopting less transistor namely to achieve the bilateral scanning function of gate driver circuit.
Accompanying drawing explanation
Fig. 1 exemplarily describes the gate drive unit circuit figure of the embodiment of the present invention one;
Fig. 2 exemplarily describes forward (Fig. 2 a) and oppositely (Fig. 2 b) scanning sequence figure of the gate drive unit circuit shown in Fig. 1;
Fig. 3 exemplarily describes the gate driver circuit block diagram be made up of the gate drive circuit unit in embodiment one;
Fig. 4 exemplarily describes gate driver circuit forward shown in Fig. 3 (Fig. 4 a) and oppositely (Fig. 4 b) scanning sequence figure;
Fig. 5 exemplarily describes the gate drive unit circuit of the embodiment of the present invention two;
Fig. 6 exemplarily describes gate drive unit circuit forward shown in Fig. 5 (Fig. 6 a) and oppositely (Fig. 6 b) scanning sequence figure;
Fig. 7 exemplarily describes the gate driver circuit block diagram be made up of the gate drive circuit unit in embodiment two;
Fig. 8 exemplarily describes gate driver circuit forward shown in Fig. 7 (Fig. 8 a) and oppositely (Fig. 8 b) scanning sequence figure;
Fig. 9 exemplarily describes the gate drive unit circuit of the embodiment of the present invention three;
Figure 10 exemplarily describes gate drive unit circuit forward shown in Fig. 9 (Figure 10 a) and oppositely (Figure 10 b) scanning sequence figure;
Figure 11 exemplarily describes the gate driver circuit block diagram be made up of the gate drive circuit unit in embodiment three;
Figure 12 exemplarily describes gate driver circuit forward shown in Figure 11 (Figure 12 a) and oppositely (Figure 12 b) scanning sequence figure.
Embodiment
For making goal of the invention of the present invention, technical scheme and advantage clearly, by reference to the accompanying drawings the present invention is described in further detail below by embodiment.
First some terms are described: with display panels (Liquid Crystal Display, LCD) be example, LCD is by two-dimensional pixel matrix, and a plurality of data lines of first direction be connected with each pel array and many controlling grid scan lines of second direction are formed.The driving circuit of LCD comprises gate driver circuit and source electrode drive circuit.Gate driver circuit produces multiple scanning pulse signal, and these scanning pulse signals are applied to the controlling grid scan line of large sequence number number successively from the controlling grid scan line of little sequence number number, be called the forward scan of gate driver circuit; These scanning pulse signals are applied to the controlling grid scan line of little sequence number number from the controlling grid scan line of large sequence number number, are called the reverse scan of gate driver circuit.Gate driver circuit can be selected to carry out forward scan or reverse scan under the control of control circuit, is called the bilateral scanning of gate driver circuit.Source electrode drive circuit is used for while gated sweep signal is applied to controlling grid scan line, source signal being applied to data line, to realize the display of FPD epigraph.
The inventive concept that the embodiment of the present application realizes bilateral scanning gate driver circuit is:
(1) driver module, the low level maintenance module of multiplexing two-way gate drive circuit unit, namely forward scan or reverse scan all adopt identical driver module, low level to maintain module; Load module, under control signal effect, accepts forward scan input signal or reverse scan input signal.Thus under forward or reverse scan pattern, the utilization factor of circuit module is all 100%, adopts less transistor namely to achieve bilateral scanning function.
(2) cooperation of forward scan control signal and reverse scan control signal is effectively utilized, can allow the lower trombone slide negative bias maintaining low level stabilization, thus make after working long hours, the threshold voltage shift of lower trombone slide is recovered, and this can strengthen the stability of gate driver circuit, extend the life-span of gate driver circuit.
In addition, the transistor in the application can be bipolar transistor or field effect transistor.When transistor is bipolar transistor, it controls the base stage that pole refers to bipolar transistor, and first end can be collector or the emitter of bipolar transistor, and the second corresponding end can be emitter or the collector of bipolar transistor; When transistor is field effect transistor, it controls the grid that pole refers to field effect transistor, and first end can be drain electrode or the source electrode of field effect transistor, and the second corresponding end can be source electrode or the drain electrode of field effect transistor.Transistor in display device is generally thin film transistor (TFT) (TFT), and the control pole of transistor refers to the grid of thin film transistor (TFT) in such cases, and first end and the second end refer to drain electrode and the source electrode of thin film transistor (TFT) respectively.
Be field effect transistor below with transistor for example describes drive element of the grid in detail.
Embodiment one:
As shown in Figure 1, be a kind of gate drive unit circuit figure of the present invention, comprise: load module 11, driver module 13, low level maintain module 12, forward scan control signal input end V
dF, reverse scan control signal input end V
dBwith signal output part V
o.
Forward scan control signal input end V
dFfor inputting forward scan control signal; Reverse scan control signal input end V
dBfor inputting reverse scan control signal; Signal output part V
ofor exporting gated sweep signal.
Load module 11 comprises the first switch module 111 and second switch module 112, first switch module 111 comprises the first signal input part, secondary signal input end and transistor T
1, the first signal input part connects the first transistor T
1grid, for receiving input first pulse signal V
i1(hereinafter referred to as the first pulse signal V
i1or the first signal input part V
i1), secondary signal input end is coupled to forward scan control signal input end V
dFand connect the first transistor T
1first end (such as drain), for receiving forward scan control signal V
dF, the output terminal of the first switch module 111 connects the first transistor T
1the second end (such as source electrode), the first transistor T
1the second end (such as source electrode) be coupled to the first Controlling vertex Q; Second switch module 112 comprises the 3rd signal input part, the 4th signal input part and transistor seconds T
2, the 3rd signal input part connects transistor seconds T
2grid, for receiving the second pulse signal V
12(hereinafter referred to as the second pulse signal V
i2or the 3rd signal input part V
i2), the 4th signal input part is coupled to reverse scan control signal input end V
dBand connect transistor seconds T
2first end (such as drain), for receiving reverse scan control signal V
dB, transistor seconds T
2the second end (such as source electrode) be coupled to the first Controlling vertex Q, the output terminal of the first switch module 111 is connected with the output terminal of second switch module 112, carries out charge or discharge to the first Controlling vertex Q, to control unlatching or the shutoff of driver module 13.
The control end of driver module 13 is coupled to the first Controlling vertex Q, and input end is for inputting the first clock signal V
a, output terminal is coupled to signal output part V
o, driver module 13 under the control of the first Controlling vertex Q, by the first clock signal V
abe applied to signal output part V
o; In the present embodiment, driver module 13 can comprise third transistor T
3with the first electric capacity C
1, third transistor T
3first end (such as drain) connect the first clock signal V
ainput end, grid connects the first Controlling vertex Q, the second end (such as source electrode) connection signal output terminal V
o, for after being opened by driving voltage, as the first clock signal V
ahigh level arrive time to signal output port V
ocharging, as the first clock signal V
alow level to pull down signal output port V when arriving
ocurrent potential; First electric capacity C
1be connected to third transistor T
3grid and signal output part V
obetween; First electric capacity C
1main Function be bootstrapping in order to realize node Q.Q point is charged to high level V in pre-charging stage
h-V
t, now third transistor T
3be opened, but due to third transistor T
3the clock signal V that connects of first end (such as drain)
afor low level, so export V
ofor low level V
l, the first electric capacity C
1charged and both end voltage difference for V
h-V
t-V
l.When the pull-up stage, V
asaltus step is high level V
h, so V
obe gradually charged high level, but due to C
1the voltage at two ends cannot suddenly change, so Q point current potential is by the level 2V booting higher
h-V
t-V
l, can T be strengthened
3driving force, make T
3be operated in linear zone, by clock signal V
athat loses without threshold value is delivered to V
o.
Forward scan control signal in the present embodiment, reverse scan control signal, the first pulse signal V
i1, the second pulse signal V
12with the first clock signal V
abe configured to: during forward scan, forward scan control signal is high level, and reverse scan control signal is low level, the first pulse signal V
i1during arrival, the first clock signal V
afor low level, as the first pulse signal V
i1after becoming the low level T/3 time, the first clock signal V
abecome high level, the second pulse signal V
12delayed first pulse signal V
i1the time of 4T/3; During reverse scan, reverse scan control signal is high level, and forward scan clock control signal is low level, the second pulse signal V
12during arrival, the first clock signal V
afor low level, as the second pulse signal V
12after becoming the low level T/3 time, the first clock signal V
abecome high level, the first pulse signal V
i1delayed second pulse signal V
12the time of 4T/3; First clock signal V
abe the cycle be T, dutycycle is the clock signal of 33%, the first pulse signal V
i1with the second pulse signal V
12pulsewidth be T/3, wherein T>0; First pulse signal V
i1with the second pulse signal V
12cycle identical with frame-scan period, frame-scan period be gate driver circuit scanning one-period time.
Low level maintains module 12 by the first Controlling vertex Q and signal output part V
obe stabilized in low level.After the first Controlling vertex Q is discharged, described low level maintains module 12 by the first Controlling vertex Q and signal output part V
obe coupled to low level until next first Controlling vertex Q is charged.In the present embodiment, low level maintains module 12 and comprises the 14 transistor T
14, the 15 transistor T
15, the 16 transistor T
16, the 17 transistor T
17, the 18 transistor T
18, the first voltage source V
sSand second voltage source V
dD, wherein the 14 transistor T
14first end (such as drain) be connected to the second voltage source V with grid
dDon, the 14 transistor T
14the second end (such as source electrode) and the 17 transistor T
17first end (such as drain) be coupled to the second Controlling vertex Q
b; 15 transistor T
15first end (such as drain) connection signal output terminal V
o, the 15 transistor T
15grid connect the 4th transistor T
14the second end (such as source electrode), the 15 transistor T
15the second end (such as source electrode) connect the first voltage source V
sS; 16 transistor T
16first end (such as drain) be connected to the first Controlling vertex Q, the 16 transistor T
16grid connect the 14 transistor T
14the second end (such as source electrode), the 16 transistor T
16the second end (such as source electrode) connect the first voltage source V
sS; 17 transistor T
17grid connect the first Controlling vertex Q, the 17 transistor T
17the second end (such as source electrode) connect the first voltage source V
sS; 18 transistor T
18first end connect the first Controlling vertex Q, the 18 transistor T
18grid connect the first clock signal V
ainput end, the 18 transistor T
18the second end connection signal output terminal V
o, the first voltage source V
sSfor low level, the second voltage source V
dDfor high level.
Fig. 2 describe the gate drive unit circuit shown in Fig. 1 forward (Fig. 2 a) and oppositely (Fig. 2 b) scanning sequence figure, the forward scan of above-mentioned gate drive circuit unit (Fig. 2 a) and the course of work of reverse scan (Fig. 2 b) be divided into four-stage: preliminary filling stage (t
1), pull-up stage (t
2), drop-down stage (t
3, t
4) and low level maintenance stage (t
5).For this circuit unit, low level maintenance stage t
5starting point be t
4terminal, t
5terminal be then t in Fig. 2 of same sequential in the next frame time
1starting point.
Illustrate the course of work of this four-stage below:
Forward scan:
(1) pre-charging stage t
1
In pre-charging stage, forward scan control signal V
dF, the first input signal V
i1be high level, so the first transistor T
1open, the current potential of node Q rises gradually, when the current potential of node Q is higher than third transistor T
3threshold voltage V
ttime, third transistor T
3be opened.Because the first clock signal V
afor low level, so output signal V
oremain low level.Precharge finish time, the current potential of node Q reaches V
h-V
t.
(2) pull-up stage (t
2)
During the pull-up stage, the first input signal V
i1for low level, the first transistor T
1turn off, Q node suspends, third transistor T
3remain opening.Clock signal V
abecome high level, and by third transistor T
3charging current is provided, output signal V to load
orise to V gradually
h.Due to third transistor T
3the raw electric capacity C of first end (such as drain)
gSwith electric capacity C
1in have electric charge, the voltage at electric capacity two ends can not suddenly change, thus the current potential of node Q can along with output signal V
orise simultaneously, finally reach 2V
h-V
t-V
l.In the pull-up stage, third transistor T
3work in linear conducting district, so clock signal V
ahigh level can be delivered to output interface V with losing without threshold value
o.
(3) drop-down stage (t
3, t
4)
The drop-down stage comprises two continuous print processes, first process t
3to output interface V
oelectric discharge.Clock signal V
abecome low level, and third transistor T
3be held open state, so output signal V
ocurrent potential by third transistor T
3pull down to low level.
Second process t in drop-down stage
4it is the electric discharge to node Q.Second input signal V
i2become high level, reverse scan signal V
dBfor low level, so transistor seconds T
2open, the stored charge of node Q is by transistor seconds T
2release, therefore the current potential of node Q reduces.When the current potential of node Q is reduced to V
tbelow, third transistor T
3turn off.
The electric charge that node Q stores must at clock signal V
alow period between thoroughly discharge, otherwise, third transistor T
3still opening is in, thus signal output interface V
olow level state at clock signal V
adestroyed under the high level effect of next cycle.
(4) low level maintenance stage (t
5)
At low level maintenance stage t
5, the 14 transistor T
14by Q
bbe charged to high level, thus the 15 transistor T
15with the 16 transistor T
16open, by node Q and signal output node V
obe stabilized in the first voltage source V
sSlow level.In addition, the 18 transistor T
18also playing and maintaining Controlling vertex Q is low level effect, because the voltage jump on Controlling vertex Q is mainly by third transistor T
3gate-drain parasitic electric capacity C
gDcause.And on Controlling vertex Q voltage jump amount mainly by third transistor T
3gate-drain parasitic electric capacity C
gDdetermine with the ratio of electric capacity on Controlling vertex Q.As the first clock signal V
awhen becoming high level, the 15 transistor T
15open, therefore Controlling vertex Q is coupled to signal output port V
o.Notice signal output port V
obe coupled to larger load capacitance C
l, therefore stray capacitance C
gDbe greatly reduced with the ratio of electric capacity on Controlling vertex Q, like this can current potential preferably on stability contorting node Q.
In the present embodiment, the pull-up stage (t of reverse scan
2), drop-down stage (t
3), low level maintenance stage (t
5) course of work of the course of work and forward scan is similar, no longer repeat here, difference is:
Preliminary filling stage t
1, in pre-charging stage, because reverse scan control signal V
dBwith the 3rd input signal V
i2for high level, so transistor seconds T
2open, the current potential of node Q rises gradually; When the current potential of node Q is higher than third transistor T
3threshold voltage V
ttime, third transistor T
3be opened.Because the first clock signal V
afor low level, so output signal V
oremain low level.Precharge finish time, the current potential of node Q reaches V
h-V
t.
Drop-down stage t
4, forward scan signal V
dFfor low level, the first input signal V
i1become high level, so the first transistor T
1open, the stored charge of node Q is by the first transistor T
1release, therefore the current potential of node Q reduces.When the current potential of node Q is reduced to V
tbelow, third transistor T
3turn off.
What Fig. 3 was exemplary describes a kind of gate driver circuit of the present invention, and this gate driver circuit is formed by the two-way gate drive circuit unit cascade shown in N level Fig. 1.
This gate driver circuit comprises the first clock cable CK
1, second clock signal wire CK
2, the 3rd clock cable CK
3, the first voltage source signal line V
sS 1, the second voltage source signal line V
dD 2, forward scan control signal wire V
dDF, reverse scan control signal wire V
dDB, and the gate drive circuit unit of multi-stage cascade as above in the present embodiment.Wherein, the first signal input part V of n-th grade of gate drive circuit unit
i1with the output signal end V of the n-th-2 grades gate driver circuits
oconnect, the 3rd signal input part V of n-th grade of gate drive circuit unit
i2with the output signal end V of the n-th+2 grades gate driver circuits
oconnect (n, N are natural number, and n<N); In all gate drive circuit units, forward scan control signal input end V
dFwith forward scan signal wire V
dDFconnect; Reverse scan control signal input end V in all gate drive circuit units
dBwith reverse scan signal wire V
dDBconnect; The first voltage source signal end V in all gate drive circuit units
sSwith the first voltage source signal line V
sS 1connect; The second voltage source signal end V in all gate drive circuit units
dDwith the second voltage source signal line V
dD 2connect; The first clock signal input terminal V in all gate drive circuit units
asuccessively and the connection first clock cable CK that circulates
1, second clock signal wire CK
2, the 3rd clock cable CK
3.
The sequential chart of gate driver circuit shown in Fig. 3 is respectively as shown in Fig. 4 a (forward scan) and Fig. 4 b (reverse scan).Sequential chart in Fig. 4 comprises three phase clock signal CK
1, CK
2, CK
3, forward scan control signal V
dDF, reverse scan control signal V
dDB, first voltage source signal line export voltage V
sS 1, second voltage source signal line export voltage V
dD 2, n-th grade of output signal V
n o, (n+1)th grade of output signal V
n+1 o, the n-th+2 grades output signal V
n+2 o, the n-th+3 grades output signal V
n+3 o, wherein the three phase clock signal period is T, and dutycycle is 33%.During forward scan, forward scan control signal V
dDFfor high level V
h, reverse scan control signal V
dDBfor low level V
l, clock signal C K
1than clock signal C K
2the time of advanced T/3, clock signal C K
1than clock signal C K
3the time of advanced 2T/3; During reverse scan, reverse scan control signal V
dDBfor high level V
h, forward scan control signal V
dDFfor low level V
l, clock signal C K
1than clock signal C K
2the time of delayed T/3, clock signal C K
1than clock signal C K
3the time of delayed 2T/3.The voltage V that first voltage source signal line exports
sS 1for low level V
l, the voltage V that the second voltage source signal line exports
dD 2for high level V
h.
The present embodiment is by driver module, the low level maintenance module of multiplexing gate drive circuit unit, namely forward scan or reverse scan all adopt identical driver module, low level to maintain module, load module, under control signal effect, accepts forward scan input signal or reverse scan input signal.Thus under forward or reverse scan pattern, the utilization factor of circuit module is all 100%, less transistor (only having 8 transistors in the present embodiment) is adopted namely to achieve bilateral scanning function.And by the cooperation of sequential, utilize single driving tube (third transistor T
3) pull-up and drop-down that outputs signal can be realized, without the need to arranging the lower trombone slide of output signal, further reduce the transistor size of two-way gate drive circuit unit.In addition the size due to driving tube is usually larger, and namely driving force is stronger, so the fall time of output signal also can reduce greatly.
Embodiment two:
In the present embodiment, the circuit diagram of gate drive circuit unit as shown in Figure 5, comprises load module 51, driver module 53, low level maintenance module 52, forward scan control signal input end V
dF, reverse scan control signal input end V
dBwith signal output part V
o.Load module 51(comprises the first switch module 511 and second switch module 512) can be identical with the load module 11 in embodiment 1, driver module 13 with driver module 53.
Forward scan control signal input end V
dFfor inputting forward scan control signal; Reverse scan control signal input end V
dBfor inputting reverse scan control signal; Signal output part V
ofor exporting gated sweep signal.
In the present embodiment, low level maintains module 52 by the first Controlling vertex Q and signal output part V
obe stabilized in low level.After the first Controlling vertex Q is discharged, low level maintains module 52 by the first Controlling vertex Q and signal output part V
obe coupled to low level until next first Controlling vertex Q is charged.Low level maintains module 52 and comprises the 24 transistor T
24, the 25 transistor T
25, the 26 transistor T
26, the 27 transistor T
27, the 28 transistor T
28and the second electric capacity C
2, wherein the second electric capacity C
2be connected to the first clock signal input terminal V of driver module 53
awith the 25 transistor T
25first end (such as drain) between; 24 transistor T
24first end (such as drain) connect third transistor T
3grid, the 24 transistor T
24grid connect the first clock signal V
ainput end, the 24 transistor T
24the second end (such as source electrode) connection signal output terminal V
o; 25 transistor T
25grid connection signal output terminal V
o, the 25 transistor T
25the second end (such as source electrode) connect the first voltage source; 26 transistor T
26first end (such as drain) connection signal output terminal V
o, the 26 transistor T
26grid connect the 25 transistor T
25first end (such as drain), the 26 transistor T
26the second end (such as source electrode) connect the first voltage source V
sS; 27 transistor T
27first end (such as drain) connection signal output terminal V
o, the 27 transistor T
27grid connect second clock signal V
binput end, the 27 transistor T
27the second end (such as source electrode) connect the first voltage source V
sS; 28 transistor T
28first end (such as drain) connection signal output terminal V
o, the 28 transistor T
28grid connect the 3rd clock signal V
cinput end, the 28 transistor T
28the second end (such as source electrode) connect the first voltage source V
sS.
Forward scan control signal in the present embodiment, reverse scan control signal, the first pulse signal, the second pulse signal and three-dimensional clock signal are configured to: during forward scan, forward scan control signal is high level, reverse scan control signal is low level, the first pulse signal V
i1during arrival, the first clock signal V
afor low level, as the first pulse signal V
i1after becoming the low level T/3 time, the first clock signal V
abecome high level, the second pulse signal V
i2delayed described first pulse signal V
i1the time of 4T/3, second clock signal V
b, the 3rd clock signal V
cdelayed first clock signal V respectively
athe time of T/3,2T/3; During reverse scan, reverse scan control signal is high level, and forward scan clock control signal is low level, the second pulse signal V
i2during arrival, the first clock signal V
afor low level, as the second pulse signal V
i2after becoming the low level T/3 time, the first clock signal V
abecome high level, the first pulse signal V
i1the time of delayed second pulse signal 4T/3, second clock signal V
b, the 3rd clock signal V
cadvanced first clock signal V respectively
athe time of T/3,2T/3; First clock signal V
a, second clock signal V
b, the 3rd clock signal V
care all cycles be T, dutycycle is the clock signal of 33%, the first pulse signal V
i1with the second pulse signal V
bpulsewidth be T/3, wherein T>0, the first voltage source V
sScurrent potential be low level.
In the present embodiment, the forward scan of gate drive circuit unit is as shown in Figure 5 similar to the course of work shown in the sequential chart 2 implementing gate drive circuit unit shown in Fig. 1 in 1 to the course of work of reverse scan sequential chart 6 (a), Fig. 6 (b), is also divided into four-stage: preliminary filling stage (t
1), pull-up stage (t
2), drop-down stage (t
3, t
4) and low level maintenance stage (t
5), no longer repeat here.Here the 25 transistor T is defined
25first end and the 6th transistor T
26the tie point of grid be Q
bnode.
Wherein, at low level maintenance stage t
5in, the present embodiment is at the first clock signal V
aduring for high level, by the second electric capacity C
2by the first clock signal V
abe coupled to Q
bnode, the 26 transistor T
26open, will V be outputed signal
opull down to the first voltage source V
sSlow level, simultaneously the first clock signal V
aduring for high level, the 24 transistor T
24open, by the ground of node Q to signal output part V
oelectronegative potential.As second clock signal V
bduring for high level, the 27 transistor T
27open, by output node V
opull down to the first voltage source V
sSelectronegative potential.As the 3rd clock signal V
cduring for high level, the 28 transistor T
28open, by output node V
opull down to the first voltage source V
sSelectronegative potential.
What Fig. 7 was exemplary describes a kind of gate driver circuit of the present invention, and this gate driver circuit is formed by the two-way gate drive circuit unit cascade shown in N level Fig. 5.This gate driver circuit comprises the first clock cable CK
1, second clock signal wire CK
2, the 3rd clock cable CK
3, the first voltage source signal line V
sS 1, forward scan control signal wire V
dDF, reverse scan control signal wire V
dDB, and the gate drive circuit unit of multi-stage cascade in the present embodiment as above, wherein, the first signal input part V of n-th grade of gate drive circuit unit
i1with the output signal end V of the n-th-2 grades gate driver circuits
oconnect, the 3rd input signal end V of n-th grade of gate drive circuit unit
i2with the output signal end V of the n-th+2 grades gate driver circuits
oconnect (n, N are natural number, and n<N); In all gate drive circuit units, forward scan control signal input end V
dFwith forward scan signal wire V
dDFconnect; Reverse scan control signal input end V in all gate drive circuit units
dBwith reverse scan signal wire V
dDBconnect; The first voltage source signal end V in all gate drive circuit units
sSwith the first voltage source signal line V
sS 1connect; The second voltage source signal end V in all gate drive circuit units
dDwith the second voltage source signal line V
dD 2connect; The first clock signal input terminal V in all gate drive circuit units
asuccessively and the connection first clock cable CK that circulates
1, second clock signal wire CK
2, the 3rd clock cable CK
3; Second clock signal input part V in all gate drive circuit units
balso circulation connects second clock signal wire CK successively
2, the 3rd clock cable CK
3, the first clock cable CK
1; The 3rd clock signal input terminal V in all gate drive circuit units
csuccessively and connection the 3rd clock cable CK that circulates
3, the first clock cable CK
1, second clock signal wire CK
2.
The sequential chart of two-way gate driver circuit shown in Fig. 7 is respectively as shown in Fig. 8 a (forward scan) and Fig. 8 b (reverse scan).Sequential chart comprises three phase clock signal (CK
1, CK
2, CK
3), forward scan control signal V
dDF, reverse scan control signal V
dDB, first voltage source signal line export voltage V
sS 1, n-th grade of output signal V
n o, (n+1)th output signal V
n+1 o, the n-th+2 grades output signal V
n+2 o, the n-th+3 grades output signal V
n+3 o, wherein the three phase clock signal period is T, and dutycycle is 33%.During forward scan, forward scan control signal V
dDFfor high level V
h, reverse scan signal V
dDBfor low level V
l, clock signal C K
1than clock signal C K
2the time of advanced T/3, clock signal C K
1than clock signal C K
3the time of advanced 2T/3.During reverse scan, reverse scan control signal V
dDBfor high level V
h, forward scan control signal V
dDFfor low level V
l, clock signal C K
1than clock signal C K
2the time of delayed T/3, clock signal C K
1than clock signal C K
3the time of delayed 2T/3.The voltage V that first voltage source signal line exports
sS 1for low level V
l.
In the present embodiment, less transistor is used to achieve the bilateral scanning function of gate driver circuit.In addition, low level maintains module 53 and adopts three transistor (T
26, T
27, T
28) under the control of three clock signals, alternately output signal 100% ground is stabilized in the first voltage source V
sSlow level, the grid-source bias voltage of three transistors to be dutycycles be 33% interchange clock signal, therefore the TFT device threshold voltage drift that maintains in module 53 of low level is less, and circuit lifetime is relatively long.
Embodiment three:
In the present embodiment, gate drive circuit unit circuit diagram comprises load module 91, driver module 93, low level maintenance module 92, forward scan control signal input end V as shown in Figure 9
dF, reverse scan control signal input end V
dBwith signal output part V
o.Load module 91(comprises the first switch module 911 and second switch module 912) can be identical with the load module 11 in embodiment 1, driver module 13 with driver module 93.
Forward scan control signal input end (V
dF) for inputting forward scan control signal; Reverse scan control signal input end (V
dB) for inputting reverse scan control signal; Signal output part (V
o) for exporting gated sweep signal; Forward scan control signal in the present embodiment, reverse scan control signal, the first pulse signal V
i1, the second pulse signal V
i2and the first clock signal V
aconfiguration mode identical with the configuration mode in embodiment 1.
In the present embodiment, low-voltage maintains module 92 and comprises the first low level maintenance module M, the second low level maintenance module N and the 45 transistor (T
45), the first low level maintains module M and comprises the 34 transistor T
34, the 35 transistor T
35, the 36 transistor T
36, the 37 transistor T
37with the 38 transistor T
38, the second low level maintains module N and comprises the 39 transistor T
39, the 40 transistor T
40, the 41 transistor T
41, the 40 two-transistor T
42, the 43 transistor T
43, wherein the 34 transistor T
34first end (such as drain) and grid be coupled to forward scan control signal input end V
dF, the second end (such as source electrode) connects the 37 transistor T
37first end (such as drain); 35 transistor T
35first end (such as drain) be coupled to the first Controlling vertex Q, the 35 transistor T
35grid connect the 34 transistor T
34the second end (such as source electrode), the 35 transistor T
35the second end (such as source electrode) be coupled to reverse scan control signal input end V
dB; 36 transistor T
36first end (such as drain) connection signal output terminal V
o, the 36 transistor T
36grid connect the 34 transistor T
34the second end (such as source electrode), the 36 transistor T
36the second end (such as source electrode) be coupled to reverse scan control signal input end V
dB; 37 transistor T
37grid be coupled to the first Controlling vertex Q, the 37 transistor T
37the second end (such as source electrode) be coupled to reverse scan control signal input end V
dB; 38 transistor T
38first end (such as drain) connect the 34 transistor T
34the second end (such as source electrode), the 38 transistor T
38grid be coupled to reverse scan control signal input end V
dB, the 38 transistor T
38the second end (such as source electrode) connect the 3rd supply voltage V
sL; 39 transistor T
39first end (such as drain) and grid be coupled to reverse scan control signal input end V
dB, the 39 transistor T
39the second end (such as source electrode) connect the 40 transistor T
40first end (such as drain); 41 transistor T
41first end (such as drain) be coupled to the first Controlling vertex Q, the 41 transistor T
41grid connect the 39 transistor T
39the second end (such as source electrode), the 41 transistor T
41the second end (such as source electrode) be coupled to forward scan control signal input end V
dF; 40 two-transistor T
42first end (such as drain) be connected to signal output part V
o, the 40 two-transistor T
42grid connect the 39 transistor T
39the second end (such as source electrode), the 40 two-transistor T
42the second end (such as source electrode) be coupled to forward scan control signal input end V
dF; 40 transistor T
40grid be coupled to the first Controlling vertex Q, the 40 transistor T
40the second end (such as source electrode) be coupled to forward scan control signal input end V
dF; 43 transistor T
43first end (such as drain) connect the 39 transistor T
39the second end (such as source electrode), the 43 transistor T
43grid be coupled to forward scan control signal input end V
dF, the 43 transistor T
43the second end (such as source electrode) connect tertiary voltage source V
sL; 45 transistor T
45first end (such as drain) connect the first Controlling vertex Q, the 45 transistor T
45grid connect the first clock signal input terminal (V
a), the 45 transistor T
45the second end (such as source electrode) connection signal output terminal V
o; Tertiary voltage source V
sLcurrent potential be low level.
In the present embodiment, the forward scan of drive circuit unit is as shown in Figure 9 similar to the course of work shown in the sequential chart 2 implementing drive circuit unit shown in Fig. 1 in 1 to the course of work of reverse scan sequential Figure 10 (a), Figure 10 (b), is also divided into four-stage: preliminary filling stage (t
1), pull-up stage (t
2), drop-down stage (t
3, t
4) and low level maintenance stage (t
5), no longer repeat here.Here the 34 transistor T is defined
34the second end (such as source electrode) and the 37 transistor T
37the tie point of first end (such as draining) is Q
b1node, the 39 transistor T
39the second end (such as source electrode) and the 40 transistor T
40the tie point of first end (such as drain) be Q
b2node.
Wherein, low level maintenance stage t
5in, during forward scan, the first low level maintains module M and works in low level maintenance state, forward scan control signal V
dFfor high level, by the 34 transistor T
34by node Q
b1be charged to high level, the 35 transistor T
35with the 36 transistor T
36open, by Q node and output signal node V
obe stabilized in reverse scan control signal V
dBlow level; Second low level maintains module N and works in threshold voltage recovering state, forward scan control signal V
dFfor high level, so the 43 transistor T
43open, by node Q
b2pull down to tertiary voltage source V
sLlow level V
s, due to the 41 transistor T
41with the 40 two-transistor T
42drain electrode be electronegative potential V
l, grid potential is V
s, source potential is V
h, V
s<V
l<V
h, so the 41 transistor T
41with the 40 two-transistor T
42work in reverse-biased, threshold voltage can recover.Low level maintenance stage t
5in, during reverse scan, the first low level maintains module M and works in threshold voltage recovering state, and the second low level maintains module N and works in low level maintenance state, similar when the course of work and forward scan, no longer repeats here.
What Figure 11 was exemplary describes a kind of driving circuit of the present invention, and this driving circuit forms by the drive circuit in bi-directional shown in N level Fig. 9 is unit cascaded.
This gate driver circuit comprises the first clock cable CK
1, second clock signal wire CK
2, the 3rd clock cable CK
3, tertiary voltage source signal line V
sS 3, forward scan control signal wire V
dDF, reverse scan control signal wire V
dDBand the described above gate drive circuit unit of multi-stage cascade in the present embodiment, wherein, the first signal input part V of n-th grade of gate drive circuit unit
i1with the output signal end V of the n-th-2 grades gate driver circuits
oconnect, the 3rd input signal end V of n-th grade of gate drive circuit unit
i2with the output signal end V of the n-th+2 grades gate driver circuits
oconnect (n, N are natural number, and n<N); In all gate drive circuit units, forward scan control signal input end V
dFwith forward scan signal wire V
dDFconnect; Reverse scan control signal input end V in all gate drive circuit units
dBwith reverse scan signal wire V
dDBconnect; Tertiary voltage source signal end V in all gate drive circuit units
sLwith tertiary voltage source signal line V
sS 3connect; The first clock signal input terminal V in all gate drive circuit units
asuccessively and the connection first clock cable CK that circulates
1, second clock signal wire CK
2, the 3rd clock cable CK
3.
The sequential chart of two-way gate driver circuit shown in Figure 11 is respectively as shown in Figure 12 a (forward scan) and Figure 12 b (reverse scan).Sequential chart comprises three phase clock signal CK
1, CK
2, CK
3, forward scan control signal V
dDF, reverse scan control signal V
dDB, tertiary voltage source signal line export voltage V
sS 3, n-th grade of output signal V
n o, (n+1)th output signal V
n+1 o, the n-th+2 grades output signal V
n+2 o, the n-th+3 grades output signal V
n+3 o, wherein CK
1, CK
2, CK
3the three phase clock signal period is T, and dutycycle is 33%.During forward scan, forward scan control signal V
dDFfor high level V
h, reverse scan signal V
dDBfor low level V
l, clock signal C K
1than clock signal C K
2the time of advanced T/3, clock signal C K
1than clock signal C K
3the time of advanced 2T/3.During reverse scan, reverse scan control signal V
dDBfor high level V
h, forward scan control signal is low level V
l, clock signal C K
1than clock signal C K
2the time of delayed T/3, clock signal C K
1than clock signal C K
3the time of delayed 2T/3, the voltage V that tertiary voltage source signal line exports
sS 3for low level V
s, and V
s<V
l.
In the present embodiment, low level maintains the identical submodule (M, N) of two circuit structures of module (93) under the control of forward and reverse scan control signal, wherein to maintain module identical for a module and the low level in embodiment one, realize low level and maintain function, and another module, driver module control end and stable output signal are in reverse-biased in low level two lower trombone slides, and threshold voltage can recover, and realizes the threshold voltage recovering function of device.When direction of scanning changes, then the duty of two submodules changes, and namely originally realizes low level and maintains the module of function to realize the recovery of device threshold voltage, and the module being originally used for realizing device threshold voltage recovery then realizes low level and maintains function.The device threshold voltage drift problem that low-voltage maintains module is improved, and can make the work of circuit long-term stability.
Drive element of the grid in the present invention and gate driver circuit can be applied on various display, comprise liquid crystal display, organic light emitting display, electric paper display etc., this display comprises the gate driver circuit in display panel and each embodiment described above, and display panel being manufactured with the gate line of first direction and the data line of second direction, in gate driver circuit, the signal output part of drive element of the grid is coupled to the gate line corresponding with it.Above in each embodiment, two-way gate driver circuit can by amorphous silicon film transistor, polycrystalline SiTFT, oxide thin film transistor, or the thin film transistor (TFT) of other type is formed.The gate driver circuit of this bilateral scanning can be integrated on display, completes together with pel array.Gate driver circuit adopts bilateral driving, and the odd-numbered line of the pixel namely on display panel and the two-way gate drive circuit unit of even number line are placed in the both sides of panel respectively.Such benefit is, the line that inter-stage can be facilitated to output signal on the one hand, and the frame of liquid crystal display can be made on the other hand symmetrical, more very thin attractive in appearance.
Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, some simple deduction or replace can also be made, all should be considered as belonging to protection of the present invention.
Claims (9)
1. a drive element of the grid, is characterized in that, comprises load module (11), driver module (13), low level maintenance module (12), forward scan control signal input end (V
dF), reverse scan control signal input end (V
dB) and signal output part (V
o);
Described forward scan control signal input end (V
dF) for inputting forward scan control signal;
Described reverse scan control signal input end (V
dB) for inputting reverse scan control signal;
Described signal output part (V
o) for exporting gated sweep signal;
The control end of described driver module (13) is coupled to the first Controlling vertex (Q), and input end is for inputting the first clock signal (V
a), output terminal is coupled to signal output part (V
o), described driver module (13) under the control of the first Controlling vertex (Q), by the first clock signal (V
a) be applied to signal output part (V
o);
Described load module (11) comprises the first switch module (111) and second switch module (112), described first switch module (111) comprises the first signal input part and secondary signal input end, and described first signal input part is for receiving the first pulse signal (V of input
i1), described secondary signal input end is coupled to forward scan control signal input end (V
dF); Described second switch module (112) comprises the 3rd signal input part and the 4th signal input part, and described 3rd signal input part is for receiving the second pulse signal (V
i2), described 4th signal input part is coupled to reverse scan control signal input end (V
dB), the output terminal of described first switch module (111) and the output terminal of second switch module (112) are connected respectively to the first Controlling vertex (Q), charge or discharge are carried out to the first Controlling vertex (Q), to control unlatching or the shutoff of driver module (13);
Described forward scan control signal, reverse scan control signal, the first pulse signal (V
i1), the second pulse signal (V
i2) and the first clock signal (V
a) being configured to: during forward scan, described forward scan control signal is high level, and described reverse scan control signal is low level, described first pulse signal (V
i1) arrive time, described first clock signal (V
a) be low level, as described first pulse signal (V
i1) become the low level T/3 time after, described first clock signal (V
a) become high level, described second pulse signal (V
i2) delayed described first pulse signal (V
i1) time of 4T/3; During reverse scan, described reverse scan control signal is high level, and described forward scan control signal is low level, described second pulse signal (V
i2) arrive time, described first clock signal (V
a) be low level, as described second pulse signal (V
i2) become the low level T/3 time after, described first clock signal (V
a) become high level, described first pulse signal (V
i1) delayed described second pulse signal (V
i2) time of 4T/3; Described first clock signal (V
a) be the cycle be T, dutycycle is the clock signal of 33%, the first pulse signal (V
i1) and the second pulse signal (V
i2) pulsewidth be T/3, wherein T>0;
Described low level maintains module (12) by the first Controlling vertex (Q) and signal output part (V
o) be stabilized in low level, after the first Controlling vertex (Q) is discharged, described low level maintains module (12) by the first Controlling vertex (Q) and signal output part (V
o) be coupled to low level until next first Controlling vertex (Q) is charged;
Described low level maintains module (12) and comprises the 14 transistor (T
14), the 15 transistor (T
15), the 16 transistor (T
16), the 17 transistor (T
17), the 18 transistor (T
18), the first voltage source (V
sS) and the second voltage source (V
dD), wherein said 14 transistor (T
14) first end with control pole be connected respectively to (V on the second voltage source
dD), the 14 transistor (T
14) the second end be coupled to described 17 transistor (T
17) first end; Described 15 transistor (T
15) first end connection signal output terminal (V
o), the 15 transistor (T
15) control pole connect described 14 transistor (T
14) the second end, the 15 transistor (T
15) the second end connect the first voltage source (V
sS); Described 16 transistor (T
16) first end be connected to the first Controlling vertex (Q), the 16 transistor (T
16) control pole connect described 14 transistor (T
14) the second end, the 16 crystal (T
16) the second end of pipe connects the first voltage source (V
sS); Described 17 transistor (T
17) control pole connect the first Controlling vertex (Q), the 17 transistor (T
17) the second end connect the first voltage source (V
sS); Described 18 transistor (T
18) first end connect the first Controlling vertex (Q), the 18 transistor (T
18) control pole connect the first clock signal (V
a) input end, the 18 transistor (T
18) the second end connection signal output terminal (V
o); Described first voltage source (V
sS) be low level, described second voltage source (V
dD) be high level.
2. a drive element of the grid, is characterized in that, comprises load module (51), driver module (53), low level maintenance module (52), forward scan control signal input end (V
dF), reverse scan control signal input end (V
dB) and signal output part (V
o);
Described forward scan control signal input end (V
dF) for inputting forward scan control signal;
Described reverse scan control signal input end (V
dB) for inputting reverse scan control signal;
Described signal output part (V
o) for exporting gated sweep signal;
The control end of described driver module (53) is coupled to the first Controlling vertex (Q), and input end is for inputting the first clock signal (V
a), output terminal is coupled to signal output part (V
o), described driver module (53) under the control of the first Controlling vertex (Q), by the first clock signal (V
a) be applied to signal output part (V
o);
Described load module (51) comprises the first switch module (511) and second switch module (512), described first switch module (511) comprises the first signal input part and secondary signal input end, and described first signal input part is for receiving the first pulse signal (V of input
i1), described secondary signal input end is coupled to forward scan control signal input end (V
dF); Described second switch module (512) comprises the 3rd signal input part and the 4th signal input part, and described 3rd signal input part is for receiving the second pulse signal (V
i2), described 4th signal input part is coupled to reverse scan control signal input end (V
dB), the output terminal of described first switch module (511) and the output terminal of second switch module (512) are connected respectively to the first Controlling vertex (Q), charge or discharge are carried out to the first Controlling vertex (Q), to control unlatching or the shutoff of driver module (53);
Described forward scan control signal, reverse scan control signal, the first pulse signal (V
i1), the second pulse signal (V
i2) and the first clock signal (V
a) being configured to: during forward scan, described forward scan control signal is high level, and described reverse scan control signal is low level, described first pulse signal (V
i1) arrive time, described first clock signal (V
a) be low level, as described first pulse signal (V
i1) become the low level T/3 time after, described first clock signal (V
a) become high level, described second pulse signal (V
i2) delayed described first pulse signal (V
i1) time of 4T/3; During reverse scan, described reverse scan control signal is high level, and described forward scan control signal is low level, described second pulse signal (V
i2) arrive time, described first clock signal (V
a) be low level, as described second pulse signal (V
i2) become the low level T/3 time after, described first clock signal (V
a) become high level, described first pulse signal (V
i1) delayed described second pulse signal (V
i2) time of 4T/3; Described first clock signal (V
a) be the cycle be T, dutycycle is the clock signal of 33%, the first pulse signal (V
i1) and the second pulse signal (V
i2) pulsewidth be T/3, wherein T>0;
Described low level maintains module (52) by the first Controlling vertex (Q) and signal output part (V
o) be stabilized in low level, after the first Controlling vertex (Q) is discharged, described low level maintains module (52) by the first Controlling vertex (Q) and signal output part (V
o) be coupled to low level until next first Controlling vertex (Q) is charged;
Described low level maintains module (52) and comprises the 24 transistor (T
24), the 25 transistor (T
25), the 26 transistor (T
26), the 27 transistor (T
27), the 28 transistor (T
28) and the second electric capacity (C
2), wherein said second electric capacity (C
2) be connected to the first clock signal input terminal (V of driver module (53)
a) and the 25 transistor (T
25) first end between; Described 24 transistor (T
24) first end connect the control pole of described driver module (53), the 24 transistor (T
24) control pole connect described first clock signal input terminal (V
a), the 24 transistor (T
24) the second end connect described signal output part (V
o); Described 25 transistor (T
25) control pole connect described signal output part (V
o), the 25 transistor (T
25) the second end connect the first voltage source (V
sS); Described 26 transistor (T
26) first end connect described signal output part (V
o), the 26 transistor (T
26) control pole connect described 25 transistor (T
25) first end, the 26 transistor (T
26) the second end connect the first voltage source (V
sS); Described 27 transistor (T
27) first end connect described signal output part (V
o), the 27 transistor (T
27) control pole connect second clock signal (V
b) input end, described second clock signal (V
b) input end is for inputting second clock signal (V
b), the 27 transistor (T
27) the second end connect the first voltage source (V
sS); Described 28 transistor (T
28) first end connect described signal output part (V
o), the 28 transistor (T
28) control pole connect the 3rd clock signal (V
c) input end, described 3rd clock signal (V
c) input end is for inputting the 3rd clock signal (V
c), the 28 transistor (T
28) the second end connect the first voltage source (V
sS); Described first clock signal (V
a), second clock signal (V
b) and the 3rd clock signal (V
c) be all identical clock signal of cycle and dutycycle, during forward scan, described second clock signal (V
b), the 3rd clock signal (V
c) the delayed described first clock signal (V of difference
a) time of T/3,2T/3, during reverse scan, described second clock signal (V
b), the 3rd clock signal (V
c) difference described first clock signal (V in advance
a) time of T/3,2T/3, the current potential (V of the first voltage source
sS) be low level.
3. a drive element of the grid, is characterized in that, comprises load module (91), driver module (93), low level maintenance module (92), forward scan control signal input end (V
dF), reverse scan control signal input end (V
dB) and signal output part (V
o);
Described forward scan control signal input end (V
dF) for inputting forward scan control signal;
Described reverse scan control signal input end (V
dB) for inputting reverse scan control signal;
Described signal output part (V
o) for exporting gated sweep signal;
The control end of described driver module (93) is coupled to the first Controlling vertex (Q), and input end is for inputting the first clock signal (V
a), output terminal is coupled to signal output part (V
o), described driver module (93) under the control of the first Controlling vertex (Q), by the first clock signal (V
a) be applied to signal output part (V
o);
Described load module (91) comprises the first switch module (911) and second switch module (912), described first switch module (911) comprises the first signal input part and secondary signal input end, and described first signal input part is for receiving the first pulse signal (V of input
i1), described secondary signal input end is coupled to forward scan control signal input end (V
dF); Described second switch module (912) comprises the 3rd signal input part and the 4th signal input part, and described 3rd signal input part is for receiving the second pulse signal (V
i2), described 4th signal input part is coupled to reverse scan control signal input end (V
dB), the output terminal of described first switch module (911) and the output terminal of second switch module (912) are connected respectively to the first Controlling vertex (Q), charge or discharge are carried out to the first Controlling vertex (Q), to control unlatching or the shutoff of driver module (93);
Described forward scan control signal, reverse scan control signal, the first pulse signal (V
i1), the second pulse signal (V
i2) and the first clock signal (V
a) being configured to: during forward scan, described forward scan control signal is high level, and described reverse scan control signal is low level, described first pulse signal (V
i1) arrive time, described first clock signal (V
a) be low level, as described first pulse signal (V
i1) become the low level T/3 time after, described first clock signal (V
a) become high level, described second pulse signal (V
i2) delayed described first pulse signal (V
i1) time of 4T/3; During reverse scan, described reverse scan control signal is high level, and described forward scan control signal is low level, described second pulse signal (V
i2) arrive time, described first clock signal (V
a) be low level, as described second pulse signal (V
i2) become the low level T/3 time after, described first clock signal (V
a) become high level, described first pulse signal (V
i1) delayed described second pulse signal (V
i2) time of 4T/3; Described first clock signal (V
a) be the cycle be T, dutycycle is the clock signal of 33%, the first pulse signal (V
i1) and the second pulse signal (V
i2) pulsewidth be T/3, wherein T>0;
Described low level maintains module (92) by the first Controlling vertex (Q) and signal output part (V
o) be stabilized in low level, after the first Controlling vertex (Q) is discharged, described low level maintains module (92) by the first Controlling vertex (Q) and signal output part (V
o) be coupled to low level until next first Controlling vertex (Q) is charged;
Described low level maintains module (92) and comprises the first low level maintenance module (M), the second low level maintenance module (N) and the 45 transistor (T
45), the first low level maintains module (M) and comprises the 34 transistor (T
34), the 35 transistor (T
35), the 36 transistor (T
36), the 37 transistor (T
37) and the 38 transistor (T
38), the second low level maintains module (N) and comprises the 39 transistor (T
39), the 40 transistor (T
40), the 41 transistor (T
41), the 40 two-transistor (T
42), the 43 transistor (T
43), wherein said 34 transistor (T
34) first end and control pole be coupled to forward scan control signal input end (V
dF), the 34 transistor (T
34) second end connect described 37 transistor (T
37) first end; Described 35 transistor (T
35) first end be coupled to the first Controlling vertex (Q), the 35 transistor (T
35) control pole connect described 34 transistor (T
34) the second end, the 35 transistor (T
35) the second end be coupled to reverse scan control signal input end (V
dB); Described 36 transistor (T
36) first end connection signal output terminal (V
o), the 36 transistor (T
36) control pole connect described 34 transistor (T
34) the second end, the 36 transistor (T
36) the second end be coupled to reverse scan control signal input end (V
dB); Described 37 transistor (T
37) control pole be coupled to the first Controlling vertex (Q), the 37 transistor (T
37) the second end be coupled to reverse scan control signal input end (V
dB); Described 38 transistor (T
38) first end connect the 34 transistor (T
34) the second end, the 38 transistor (T
38) control pole be coupled to reverse scan control signal input end (V
dB), the 38 transistor (T
38) second end connect the 3rd supply voltage (V
sL); Described 39 transistor (T
39) first end and control pole be coupled to reverse scan control signal input end (V
dB), the 39 transistor (T
39) second end connect described 40 transistor (T
40) first end; Described 41 transistor (T
41) first end be coupled to the first Controlling vertex (Q), the 41 transistor (T
41) control pole connect described 39 transistor (T
39) the second end, the 41 transistor (T
41) the second end be coupled to forward scan control signal input end (V
dF); Described 40 two-transistor (T
42) first end be connected to signal output part (V
o), the 40 two-transistor (T
42) control pole connect described 39 transistor (T
39) the second end, the 40 two-transistor (T
42) the second end be coupled to forward scan control signal input end (V
dF); Described 40 transistor (T
40) control pole be coupled to the first Controlling vertex (Q), the 40 transistor (T
40) the second end be coupled to forward scan control signal input end (V
dF); Described 43 transistor (T
43) first end connect described 39 transistor (T
39) the second end, the 43 transistor (T
43) control pole be coupled to forward scan control signal input end (V
dF), the 43 transistor (T
43) second end connect tertiary voltage source (V
sL), described 45 transistor (T
45) first end connect the first Controlling vertex (Q), the 45 transistor (T
45) control pole connect the first clock signal (V
a), the 45 transistor (T
45) the second end be connected to signal output part (V
o), described tertiary voltage source (V
sL) current potential be low level.
4. the drive element of the grid as described in any one of claim 1-3, is characterized in that, described first switch module (111,511,911) comprises the first transistor (T
1), described the first transistor (T
1) control pole be connected to the first signal input part, for receiving the first pulse signal (V of input
i1), described the first transistor (T
1) first end be coupled to forward scan control signal input end (V
dF), the first transistor (T
1) the second end be coupled to the first Controlling vertex (Q); Described second switch module (112,512,912) comprises transistor seconds (T
2), described transistor seconds (T
2) control pole be connected to the 3rd signal input part, for receiving the second pulse signal (V
i2), transistor seconds (T
2) first end be coupled to reverse scan control signal input end (V
dB), transistor seconds (T
2) the second end be coupled to the first Controlling vertex (Q).
5. the drive element of the grid as described in any one of claim 1-3, is characterized in that, described driver module comprises third transistor (T
3), described third transistor (T
3) control pole connect described first Controlling vertex (Q), described third transistor (T
3) first end connect the first clock signal (V
a) input end, for inputting the first clock signal (V
a), third transistor (T
3) the second end be coupled to signal output part (V
o).
6. drive element of the grid as claimed in claim 5, it is characterized in that, described driver module also comprises the first electric capacity (C
1), described first electric capacity (C
1) be connected to described third transistor (T
3) control pole and signal output part (V
o) between.
7. the drive element of the grid as described in any one of claim 1-3, is characterized in that, described first pulse signal is identical with frame-scan period with the cycle of the second pulse signal.
8. a gate driver circuit, it is characterized in that, comprise the gate drive circuit unit of N level cascade, gate drive circuit unit described at least one is the gate drive circuit unit described in claim 1 to claim 7 any one, first signal input part of n-th grade of gate drive circuit unit is connected with the signal output part of the n-th-2 grades gate driver circuits, 3rd signal input part of the gate drive circuit unit of n-th grade is coupled to the signal output part of the n-th+2 stage drive circuit unit, wherein N be greater than 0 integer, n is the integer being greater than 0 and being less than N.
9. a display, is characterized in that comprising:
Display panel, described display panel is manufactured with the gate line of first direction and the data line of second direction;
Driving circuit according to claim 8, in described gate driver circuit, the signal output part of drive element of the grid is coupled to the gate line corresponding with it.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210277113.7A CN102842278B (en) | 2012-08-06 | 2012-08-06 | Gate drive circuit unit, gate driver circuit and display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210277113.7A CN102842278B (en) | 2012-08-06 | 2012-08-06 | Gate drive circuit unit, gate driver circuit and display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102842278A CN102842278A (en) | 2012-12-26 |
| CN102842278B true CN102842278B (en) | 2015-09-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210277113.7A Active CN102842278B (en) | 2012-08-06 | 2012-08-06 | Gate drive circuit unit, gate driver circuit and display |
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| CN103761002B (en) * | 2013-12-31 | 2017-05-10 | 北京大学深圳研究生院 | Touch circuit, touch circuit unit, touch display panel and touch display device |
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Address after: 518055 Guangdong city in Shenzhen Province, Nanshan District City Xili Shenzhen University North Campus Co-patentee after: Kunshan Longteng Au Optronics Co. Patentee after: PEKING University SHENZHEN GRADUATE SCHOOL Address before: 518055 Guangdong city in Shenzhen Province, Nanshan District City Xili Shenzhen University North Campus Co-patentee before: Infovision Optoelectronics (Kunshan) Co.,Ltd. Patentee before: PEKING University SHENZHEN GRADUATE SCHOOL |
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