DE69132766T2 - Gatter-Adressierungssystem für eine Logiksimulationsmaschine - Google Patents

Gatter-Adressierungssystem für eine Logiksimulationsmaschine

Info

Publication number
DE69132766T2
DE69132766T2 DE69132766T DE69132766T DE69132766T2 DE 69132766 T2 DE69132766 T2 DE 69132766T2 DE 69132766 T DE69132766 T DE 69132766T DE 69132766 T DE69132766 T DE 69132766T DE 69132766 T2 DE69132766 T2 DE 69132766T2
Authority
DE
Germany
Prior art keywords
simulation engine
logic simulation
addressing system
gate addressing
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69132766T
Other languages
English (en)
Other versions
DE69132766D1 (de
Inventor
Minoru Shoji
Fumiyasu Hirose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69132766D1 publication Critical patent/DE69132766D1/de
Publication of DE69132766T2 publication Critical patent/DE69132766T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69132766T 1990-01-29 1991-01-29 Gatter-Adressierungssystem für eine Logiksimulationsmaschine Expired - Fee Related DE69132766T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1842090 1990-01-29
JP21782990 1990-08-18

Publications (2)

Publication Number Publication Date
DE69132766D1 DE69132766D1 (de) 2001-11-22
DE69132766T2 true DE69132766T2 (de) 2002-04-25

Family

ID=26355092

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69132766T Expired - Fee Related DE69132766T2 (de) 1990-01-29 1991-01-29 Gatter-Adressierungssystem für eine Logiksimulationsmaschine

Country Status (3)

Country Link
US (1) US5245549A (de)
EP (3) EP0440553B1 (de)
DE (1) DE69132766T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5500808A (en) * 1991-01-24 1996-03-19 Synopsys, Inc. Apparatus and method for estimating time delays using unmapped combinational logic networks
US5978571A (en) * 1993-03-19 1999-11-02 Digital Equipment Corporation Method and apparatus for synchronous circuit simulation design by eliminating unneeded timing behaviors prior to simulation run-time
US5648911A (en) * 1993-12-21 1997-07-15 Grodstein; Joel Joseph Method of minimizing area for fanout chains in high-speed networks
US10776543B2 (en) 2018-06-25 2020-09-15 International Business Machines Corporation Automated region based optimization of chip manufacture

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS593652A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd ハ−ド論理シミユレ−タ装置
JPS5975347A (ja) * 1982-10-21 1984-04-28 Toshiba Corp 論理回路のシミユレ−シヨン装置
JPH0743733B2 (ja) * 1985-12-11 1995-05-15 株式会社日立製作所 論理シミュレーション方法
JPS6381567A (ja) * 1986-09-26 1988-04-12 Hitachi Ltd 論理シミユレ−シヨン処理装置
JPS63204441A (ja) * 1987-02-20 1988-08-24 Fujitsu Ltd 論理シミユレ−シヨン専用プロセツサの処理方式
JP2699377B2 (ja) * 1987-02-25 1998-01-19 日本電気株式会社 ハードウエア論理シミユレータ
US4816999A (en) * 1987-05-20 1989-03-28 International Business Machines Corporation Method of detecting constants and removing redundant connections in a logic network
US5051938A (en) * 1989-06-23 1991-09-24 Hyduke Stanley M Simulation of selected logic circuit designs

Also Published As

Publication number Publication date
EP1187043A2 (de) 2002-03-13
EP1115072A2 (de) 2001-07-11
US5245549A (en) 1993-09-14
EP0440553A2 (de) 1991-08-07
EP0440553B1 (de) 2001-10-17
EP0440553A3 (de) 1994-02-16
DE69132766D1 (de) 2001-11-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee