DE69130757T2 - Ausführungsvorrichtung für bedingte Verzweigungsbefehle - Google Patents

Ausführungsvorrichtung für bedingte Verzweigungsbefehle

Info

Publication number
DE69130757T2
DE69130757T2 DE69130757T DE69130757T DE69130757T2 DE 69130757 T2 DE69130757 T2 DE 69130757T2 DE 69130757 T DE69130757 T DE 69130757T DE 69130757 T DE69130757 T DE 69130757T DE 69130757 T2 DE69130757 T2 DE 69130757T2
Authority
DE
Germany
Prior art keywords
instruction
abort
instructions
branch
condition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130757T
Other languages
German (de)
English (en)
Other versions
DE69130757D1 (de
Inventor
Takeshi C/O Intell. Property Div. Minato-Ku Tokyo 105 Aikawa
Kenji C/O Intell. Property Div. Minato-Ku Tokyo 105 Minagawa
Mitsuo C/O Intell. Property Div. Minato-Ku Tokyo 105 Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP34034790A external-priority patent/JP2835179B2/ja
Priority claimed from JP3073273A external-priority patent/JPH04308946A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69130757D1 publication Critical patent/DE69130757D1/de
Publication of DE69130757T2 publication Critical patent/DE69130757T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE69130757T 1990-11-30 1991-11-29 Ausführungsvorrichtung für bedingte Verzweigungsbefehle Expired - Fee Related DE69130757T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP34034790A JP2835179B2 (ja) 1990-11-30 1990-11-30 並列処理計算機
JP3073273A JPH04308946A (ja) 1991-04-05 1991-04-05 電子計算機

Publications (2)

Publication Number Publication Date
DE69130757D1 DE69130757D1 (de) 1999-02-25
DE69130757T2 true DE69130757T2 (de) 1999-07-29

Family

ID=26414425

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130757T Expired - Fee Related DE69130757T2 (de) 1990-11-30 1991-11-29 Ausführungsvorrichtung für bedingte Verzweigungsbefehle

Country Status (3)

Country Link
US (2) US5446849A (ref)
EP (1) EP0488819B1 (ref)
DE (1) DE69130757T2 (ref)

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US5619238A (en) * 1992-07-24 1997-04-08 Canon Kabushiki Kaisha Method of making replaceable ink cartridge
US5872945A (en) * 1993-07-26 1999-02-16 Intel Corporation MX bus translation to new system bus protocol
FR2740238B1 (fr) * 1995-10-19 1997-12-05 Sgs Thomson Microelectronics Cellule integrable ddc dediee a un microprocesseur
US5774683A (en) * 1996-10-21 1998-06-30 Advanced Micro Devices, Inc. Interconnect bus configured to implement multiple transfer protocols
US6055628A (en) * 1997-01-24 2000-04-25 Texas Instruments Incorporated Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks
US6065086A (en) * 1998-02-17 2000-05-16 International Business Machines Corporation Demand based sync bus operation
US6345355B1 (en) * 1998-05-29 2002-02-05 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for distributing commands to a plurality of circuit blocks
EP1050811A1 (en) * 1999-05-03 2000-11-08 STMicroelectronics SA Branching in a computer system
US6457119B1 (en) * 1999-07-23 2002-09-24 Intel Corporation Processor instruction pipeline with error detection scheme
US6437710B1 (en) 2000-11-10 2002-08-20 Oasis Design, Inc. Encoder within a communication system that avoids encoded DC accumulation and can use coding violations to synchronize a decoder and detect transmission errors
DE10101949C1 (de) * 2001-01-17 2002-08-08 Infineon Technologies Ag Datenverarbeitungsverfahren
EP1258803A3 (en) 2001-05-17 2007-09-05 Broadcom Corporation Cancelling instructions
FR2835677B1 (fr) * 2002-02-04 2004-04-30 Prosilog S A Perfectionnements apportes aux systemes electroniques compre nant un bus de communication
US7590819B2 (en) * 2005-05-09 2009-09-15 Lsi Logic Corporation Compact memory management unit
US7363463B2 (en) * 2005-05-13 2008-04-22 Microsoft Corporation Method and system for caching address translations from multiple address spaces in virtual machines
US8909946B2 (en) 2005-11-15 2014-12-09 Microsoft Corporation Efficient power management of a system with virtual machines
US8694712B2 (en) * 2006-12-05 2014-04-08 Microsoft Corporation Reduction of operational costs of virtual TLBs
JP5300407B2 (ja) 2008-10-20 2013-09-25 株式会社東芝 仮想アドレスキャッシュメモリ及び仮想アドレスキャッシュ方法
JP2010097557A (ja) * 2008-10-20 2010-04-30 Toshiba Corp セットアソシアティブ方式のキャッシュ装置及びキャッシュ方法
JP2011198091A (ja) * 2010-03-19 2011-10-06 Toshiba Corp 仮想アドレスキャッシュメモリ、プロセッサ及びマルチプロセッサシステム
US9317630B2 (en) 2012-12-07 2016-04-19 International Business Machines Corporation Memory frame architecture for instruction fetches in simulation
US9336341B2 (en) 2012-12-07 2016-05-10 International Business Machines Corporation Memory frame proxy architecture for synchronization and check handling in a simulator
US10019174B2 (en) * 2015-10-27 2018-07-10 Sandisk Technologies Llc Read operation delay

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4463421A (en) * 1980-11-24 1984-07-31 Texas Instruments Incorporated Serial/parallel input/output bus for microprocessor system
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
JPH083805B2 (ja) * 1985-06-28 1996-01-17 ヒューレット・パッカード・カンパニー Ｔｌｂ制御方法
US4713755A (en) * 1985-06-28 1987-12-15 Hewlett-Packard Company Cache memory consistency control with explicit software instructions
US4777587A (en) * 1985-08-30 1988-10-11 Advanced Micro Devices, Inc. System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses
US5347636A (en) * 1985-11-08 1994-09-13 Nec Corporation Data processor which efficiently accesses main memory and input/output devices
US5136696A (en) * 1988-06-27 1992-08-04 Prime Computer, Inc. High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and multicycle instructions
JP2810068B2 (ja) * 1988-11-11 1998-10-15 株式会社日立製作所 プロセッサシステム、コンピュータシステム及び命令処理方法
US5150469A (en) * 1988-12-12 1992-09-22 Digital Equipment Corporation System and method for processor pipeline control by selective signal deassertion
US5129067A (en) * 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5193206A (en) * 1989-12-27 1993-03-09 Motorola, Inc. Reduce instruction set microprocessor
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
JP2535252B2 (ja) * 1990-10-17 1996-09-18 三菱電機株式会社 並列処理装置
US5265213A (en) * 1990-12-10 1993-11-23 Intel Corporation Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction

Also Published As

Publication number Publication date
US5446849A (en) 1995-08-29
EP0488819B1 (en) 1999-01-13
US5617553A (en) 1997-04-01
DE69130757D1 (de) 1999-02-25
EP0488819A3 (ref) 1994-04-13
EP0488819A2 (en) 1992-06-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee