DE69130640D1 - Arithmetische Operationseinheit mit Bit-Invertierungsfunktion - Google Patents

Arithmetische Operationseinheit mit Bit-Invertierungsfunktion

Info

Publication number
DE69130640D1
DE69130640D1 DE69130640T DE69130640T DE69130640D1 DE 69130640 D1 DE69130640 D1 DE 69130640D1 DE 69130640 T DE69130640 T DE 69130640T DE 69130640 T DE69130640 T DE 69130640T DE 69130640 D1 DE69130640 D1 DE 69130640D1
Authority
DE
Germany
Prior art keywords
operation unit
arithmetic operation
bit inversion
inversion function
function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130640T
Other languages
English (en)
Other versions
DE69130640T2 (de
Inventor
Makoto Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69130640D1 publication Critical patent/DE69130640D1/de
Publication of DE69130640T2 publication Critical patent/DE69130640T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3852—Calculation with most significant digit first
DE69130640T 1990-12-29 1991-12-30 Arithmetische Operationseinheit mit Bit-Invertierungsfunktion Expired - Fee Related DE69130640T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2417201A JPH04230521A (ja) 1990-12-29 1990-12-29 ビット反転演算器

Publications (2)

Publication Number Publication Date
DE69130640D1 true DE69130640D1 (de) 1999-01-28
DE69130640T2 DE69130640T2 (de) 1999-07-22

Family

ID=18525327

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130640T Expired - Fee Related DE69130640T2 (de) 1990-12-29 1991-12-30 Arithmetische Operationseinheit mit Bit-Invertierungsfunktion

Country Status (4)

Country Link
US (1) US5224065A (de)
EP (1) EP0493835B1 (de)
JP (1) JPH04230521A (de)
DE (1) DE69130640T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5267187A (en) * 1990-05-10 1993-11-30 Xilinx Inc Logic structure and circuit for fast carry
KR960004572B1 (ko) * 1994-01-28 1996-04-09 금성일렉트론주식회사 산술연산 논리회로
US5442577A (en) * 1994-03-08 1995-08-15 Exponential Technology, Inc. Sign-extension of immediate constants in an alu
US7284222B1 (en) * 2004-06-30 2007-10-16 Tabula, Inc. Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit
US7282950B1 (en) * 2004-11-08 2007-10-16 Tabula, Inc. Configurable IC's with logic resources with offset connections
US7312630B2 (en) * 2004-06-30 2007-12-25 Tabula, Inc. Configurable integrated circuit with built-in turns
US7917559B2 (en) * 2004-11-08 2011-03-29 Tabula, Inc. Configurable IC's with configurable logic circuits that perform adder and/or subtractor operations
US7743085B2 (en) * 2004-11-08 2010-06-22 Tabula, Inc. Configurable IC with large carry chains
US7310003B2 (en) * 2005-03-15 2007-12-18 Tabula, Inc. Configurable IC with interconnect circuits that have select lines driven by user signals
US7825684B2 (en) * 2005-03-15 2010-11-02 Tabula, Inc. Variable width management for a memory of a configurable IC
US7530033B2 (en) 2005-03-15 2009-05-05 Tabula, Inc. Method and apparatus for decomposing functions in a configurable IC
US7298169B2 (en) * 2005-03-15 2007-11-20 Tabula, Inc Hybrid logic/interconnect circuit in a configurable IC
US20070244959A1 (en) * 2005-03-15 2007-10-18 Steven Teig Configurable IC's with dual carry chains
US7818361B1 (en) 2005-11-07 2010-10-19 Tabula, Inc. Method and apparatus for performing two's complement multiplication
US8463836B1 (en) 2005-11-07 2013-06-11 Tabula, Inc. Performing mathematical and logical operations in multiple sub-cycles
US7765249B1 (en) 2005-11-07 2010-07-27 Tabula, Inc. Use of hybrid interconnect/logic circuits for multiplication
US7694083B1 (en) * 2006-03-08 2010-04-06 Tabula, Inc. System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture
US7797497B1 (en) * 2006-03-08 2010-09-14 Tabula, Inc. System and method for providing more logical memory ports than physical memory ports
US7930666B1 (en) 2006-12-12 2011-04-19 Tabula, Inc. System and method of providing a memory hierarchy
US10756753B2 (en) * 2018-10-25 2020-08-25 Arm Limited Data compressor logic circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2610417B2 (ja) * 1985-12-23 1997-05-14 日本テキサス・インスツルメンツ株式会社 アドレス信号生成方法及びその回路
IT1210751B (it) * 1987-05-20 1989-09-20 Cselt Centro Studi Lab Telecom Sommatore veloce in tecnologia c mos
JPH01180633A (ja) * 1988-01-12 1989-07-18 Mitsubishi Electric Corp 加算器
JPH0679269B2 (ja) * 1988-05-20 1994-10-05 三菱電機株式会社 加算器
US4974188A (en) * 1988-12-09 1990-11-27 The Johns Hopkins University Address sequence generation by means of reverse carry addition

Also Published As

Publication number Publication date
EP0493835A2 (de) 1992-07-08
US5224065A (en) 1993-06-29
JPH04230521A (ja) 1992-08-19
DE69130640T2 (de) 1999-07-22
EP0493835A3 (en) 1993-05-05
EP0493835B1 (de) 1998-12-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee