DE69110456T2 - DEVICE FOR INTERLAYER PLANNING OF SEMICONDUCTORS. - Google Patents

DEVICE FOR INTERLAYER PLANNING OF SEMICONDUCTORS.

Info

Publication number
DE69110456T2
DE69110456T2 DE69110456T DE69110456T DE69110456T2 DE 69110456 T2 DE69110456 T2 DE 69110456T2 DE 69110456 T DE69110456 T DE 69110456T DE 69110456 T DE69110456 T DE 69110456T DE 69110456 T2 DE69110456 T2 DE 69110456T2
Authority
DE
Germany
Prior art keywords
semiconductors
planning
interlayer
interlayer planning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Revoked
Application number
DE69110456T
Other languages
German (de)
Other versions
DE69110456D1 (en
Inventor
Thomas Hyde
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Westech Systems Inc
Original Assignee
Westech Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23977323&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69110456(T2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Westech Systems Inc filed Critical Westech Systems Inc
Application granted granted Critical
Publication of DE69110456D1 publication Critical patent/DE69110456D1/en
Publication of DE69110456T2 publication Critical patent/DE69110456T2/en
Anticipated expiration legal-status Critical
Revoked legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B24B37/22—Lapping pads for working plane surfaces characterised by a multi-layered structure
DE69110456T 1990-03-22 1991-03-22 DEVICE FOR INTERLAYER PLANNING OF SEMICONDUCTORS. Revoked DE69110456T2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US49755190A 1990-03-22 1990-03-22
PCT/US1991/001945 WO1991014538A1 (en) 1990-03-22 1991-03-22 Apparatus for interlayer planarization of semiconductor material

Publications (2)

Publication Number Publication Date
DE69110456D1 DE69110456D1 (en) 1995-07-20
DE69110456T2 true DE69110456T2 (en) 1995-12-14

Family

ID=23977323

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69110456T Revoked DE69110456T2 (en) 1990-03-22 1991-03-22 DEVICE FOR INTERLAYER PLANNING OF SEMICONDUCTORS.

Country Status (4)

Country Link
EP (1) EP0521102B1 (en)
JP (3) JP3442772B2 (en)
DE (1) DE69110456T2 (en)
WO (1) WO1991014538A1 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5257478A (en) * 1990-03-22 1993-11-02 Rodel, Inc. Apparatus for interlayer planarization of semiconductor material
JP2513426B2 (en) * 1993-09-20 1996-07-03 日本電気株式会社 Wafer polishing machine
US5893796A (en) * 1995-03-28 1999-04-13 Applied Materials, Inc. Forming a transparent window in a polishing pad for a chemical mechanical polishing apparatus
JP3329644B2 (en) * 1995-07-21 2002-09-30 株式会社東芝 Polishing pad, polishing apparatus and polishing method
KR100189970B1 (en) * 1995-08-07 1999-06-01 윤종용 A polishing apparatus for semiconductor wafer
US5692950A (en) * 1996-08-08 1997-12-02 Minnesota Mining And Manufacturing Company Abrasive construction for semiconductor wafer modification
US6705934B1 (en) 1998-08-28 2004-03-16 Toray Industries, Inc. Polishing pad
US6666751B1 (en) 2000-07-17 2003-12-23 Micron Technology, Inc. Deformable pad for chemical mechanical polishing
JP2003100682A (en) 2001-09-25 2003-04-04 Jsr Corp Polishing pad for semiconductor wafer
JP3754436B2 (en) 2004-02-23 2006-03-15 東洋ゴム工業株式会社 Polishing pad and semiconductor device manufacturing method using the same
JP2006245445A (en) * 2005-03-07 2006-09-14 Nihon Micro Coating Co Ltd Abrasive pad
WO2008123085A1 (en) 2007-03-20 2008-10-16 Kuraray Co., Ltd. Cushion for polishing pad and polishing pad using the cushion
JP6434174B2 (en) * 2018-01-29 2018-12-05 富士紡ホールディングス株式会社 Polishing pad and manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3504457A (en) * 1966-07-05 1970-04-07 Geoscience Instr Corp Polishing apparatus
NL7101327A (en) * 1971-02-02 1972-08-04
US4132037A (en) 1977-02-28 1979-01-02 Siltec Corporation Apparatus for polishing semiconductor wafers

Also Published As

Publication number Publication date
JP3560961B2 (en) 2004-09-02
JP3442772B2 (en) 2003-09-02
JPH05505769A (en) 1993-08-26
EP0521102B1 (en) 1995-06-14
JP2004221611A (en) 2004-08-05
JP2003303794A (en) 2003-10-24
WO1991014538A1 (en) 1991-10-03
DE69110456D1 (en) 1995-07-20
JP3660933B2 (en) 2005-06-15
EP0521102A1 (en) 1993-01-07

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Legal Events

Date Code Title Description
8363 Opposition against the patent
8331 Complete revocation