DE69031011D1 - Optimierte Verbindungssysteme - Google Patents

Optimierte Verbindungssysteme

Info

Publication number
DE69031011D1
DE69031011D1 DE69031011T DE69031011T DE69031011D1 DE 69031011 D1 DE69031011 D1 DE 69031011D1 DE 69031011 T DE69031011 T DE 69031011T DE 69031011 T DE69031011 T DE 69031011T DE 69031011 D1 DE69031011 D1 DE 69031011D1
Authority
DE
Germany
Prior art keywords
way
interconnected
nodes
way interconnected
node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69031011T
Other languages
English (en)
Other versions
DE69031011T2 (de
Inventor
Kurt Baty
Charles J Horvath
Richard C Clemson
Scott J Bleiweiss
Kenneth T Wolff
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ascend Communications Inc
Original Assignee
Stratus Computer Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stratus Computer Inc filed Critical Stratus Computer Inc
Application granted granted Critical
Publication of DE69031011D1 publication Critical patent/DE69031011D1/de
Publication of DE69031011T2 publication Critical patent/DE69031011T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Stereophonic System (AREA)
  • Liquid Developers In Electrophotography (AREA)
  • Magnetic Resonance Imaging Apparatus (AREA)
DE69031011T 1989-05-19 1990-05-16 Optimierte Verbindungssysteme Expired - Fee Related DE69031011T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US35413989A 1989-05-19 1989-05-19

Publications (2)

Publication Number Publication Date
DE69031011D1 true DE69031011D1 (de) 1997-08-14
DE69031011T2 DE69031011T2 (de) 1998-02-19

Family

ID=23392024

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031011T Expired - Fee Related DE69031011T2 (de) 1989-05-19 1990-05-16 Optimierte Verbindungssysteme

Country Status (5)

Country Link
EP (1) EP0398678B1 (de)
JP (2) JPH0311455A (de)
AT (1) ATE155265T1 (de)
CA (1) CA2016193A1 (de)
DE (1) DE69031011T2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4738514B2 (ja) * 2009-07-13 2011-08-03 智基 杉本 収納かご

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2470996B1 (fr) * 1979-11-30 1986-01-31 Quinquis Jean Paul Perfectionnements aux systemes electroniques multiprocesseurs destines au traitement de donnees numeriques et logiques
US4939643A (en) * 1981-10-01 1990-07-03 Stratus Computer, Inc. Fault tolerant digital data processor with improved bus protocol

Also Published As

Publication number Publication date
JP2000000064U (ja) 2000-08-11
ATE155265T1 (de) 1997-07-15
DE69031011T2 (de) 1998-02-19
EP0398678A3 (de) 1992-09-02
JPH0311455A (ja) 1991-01-18
EP0398678B1 (de) 1997-07-09
CA2016193A1 (en) 1990-11-19
EP0398678A2 (de) 1990-11-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: KRAMER - BARSKE - SCHMIDTCHEN, 81245 MUENCHEN

8339 Ceased/non-payment of the annual fee